A 3.2 GOPS multiprocessor DSP for communication applications

Williams, J.; Singh, K.J.; Nicol, Chris; Sackinger, E.; Daubert, S.J.; Micca, E.; Moturi, M.; Knobloch, Jens; Brinthaupt, D.; Ackland, B.

doi:10.1109/isscc.2000.839695

Cited by 7 publications

(2 citation statements)

References 3 publications

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“…Often these different memory structures require different control logic and status bits. Therefore, a memory system that can be configured to closely match the application demands is desirable [27].…”

Section: Memory Systemmentioning

confidence: 99%

Smart Memories: A Modular Reconfigurable Architecture

Mai¹,

Paaske²,

Jayasena³

et al. 2000

119

104

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Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these conflicting requirements, we propose a modular reconfigurable architecture called Smart Memories, targeted at computing needs in the 0.1µm technology generation. A Smart Memories chip is made up of many processing tiles, each containing local memory, local interconnect, and a processor core. For efficient computation under a wide class of possible applications, the memories, the wires, and the computational model can all be altered to match the applications. To show the applicability of this design, two very different machines at opposite ends of the architectural spectrum, the Imagine stream processor and the Hydra speculative multiprocessor, are mapped onto the Smart Memories computing substrate. Simulations of the mappings show that the Smart Memories architecture can successfully map these architectures with only modest performance degradation.

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Section: Memory Systemmentioning

confidence: 99%

Smart Memories: A Modular Reconfigurable Architecture

Mai¹,

Paaske²,

Jayasena³

et al. 2000

119

104

View full text Add to dashboard Cite

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“…These can be executed on separate DSP processors. Integrating multiple DSP cores into a single chip is achieved using a MIMD DSP architecture like Daytona [1] [21] (shown in Figure 13) which uses a high performance split transaction bus to connect multiple DSP cores with a memory hierarchy. Each DSP core has a cache for both instructions and data -to minimize the memory connected to each DSP.…”

Section: Multi-processor Dsp Systemsmentioning

confidence: 99%

Low power DSP's for wireless communications

Verbauwhede¹,

Nicol²

2000

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

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Wireless communications and more specifically, the fast growing penetration of cellular phones and cellular infrastructure are the major drivers for the development of new programmable Digital Signal Processors (DSP's). In this tutorial, an overview will be given of recent developments in DSP processor architectures, that makes them well suited to execute computationally intensive algorithms typically found in communications systems. DSP processors have adapted instruction sets, memory architectures and data paths to execute compute intensive communications algorithms efficiently and in a low power fashion. Basic building blocks include convolutional decoders (mainly the Viterbi algorithm), turbo coding algorithms, FIR filters, speech coders, etc. This is illustrated with examples of different commercial and research processors. Please note that the authors do not endorse the processors used in this tutorial. These processors are used to illustrate how different solutions are proposed for the same problem.

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