A 3.3 Gb/s Sample Circuit with GaAs MESFET Technology and SCFL Gates

Abstract

This paper presents the implementation of the sampling technique by means of the coordinated delays' method, using the SCFL (Source Coupled FET Logic) logic in GaAs MESFET technology. This technique presents a high resolution and is based on controlling delays in the clock and in the data signal paths, by means of delay elements. The resolution is related to the difference in the delay in both paths. The delay elements are implemented by means of differential invertors, in SCFL logic. A sample circuit of 64 stages has been designed. Its operation has been simulated using the HSPICE program that resulted in a high resolution at a bit rate of 3.33 Gb/s. The circuit prototypes are being fabricated at Vitesse Semiconductor, using the H-GaAs III process with 0.6Jlm gate length. Measurement results "like maximum rate, resolution and jitter" will be presented at the meeting.