A 3.3 Gbps CCSDS 123.0-B-1 Multispectral &amp; Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA

Tsigkanos, Antonis; Kranitis, N.; Θεοδώρου, Γεώργιος; Paschalis, A.

doi:10.1109/tetc.2018.2854412

Cited by 32 publications

(27 citation statements)

References 7 publications

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“…Regarding other hardware-based alternatives in the literature, the most common approach is to generate highly optimized applicationspecific accelerators, as opposed to ARTICo 3 , which has a more general purpose (i.e., the same architecture can be used to accelerate different algorithms). For instance, in [1], a combination of task-level parallelism and a reconfigurable fine-grained pipeline is used to achieve one of the fastest implementations of the CCSDS 123 standard up to date. In addition, these implementations usually rely on designtime customization of the hardware accelerators, as opposed to ARTICo 3 , where DPR allows dynamic changes at run time.…”

Section: Resultsmentioning

confidence: 99%

“…Hyperspectral compression algorithms are usually implemented in hardware fabrics (e.g., ASICs or radiationhardened FPGAs), since they provide high-performance and low-energy solutions [1]. However, these approaches present several drawbacks: on the one hand, they lack flexibility once deployed, since it is impossible to make modifications in the implemented circuit; on the other hand, they rely on expensive space-qualified devices to ensure correct behavior during mission time.…”

Section: Introductionmentioning

confidence: 99%

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Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

et al. 2019

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Hyperspectral data processing is a computationally intensive task that is usually performed in high-performance computing clusters. However, in remote sensing scenarios, where communications are expensive, a compression stage is required at the edge of data acquisition before transmitting information to ground stations for further processing. Moreover, hyperspectral image compressors need to meet minimum performance and energy-efficiency levels to cope with the real-time requirements imposed by the sensors and the available power budget. Hence, they are usually implemented as dedicated hardware accelerators in expensive space-grade electronic devices. In recent years though, these devices have started to coexist with low-cost commercial alternatives in which unconventional techniques, such as run-time hardware reconfiguration are evaluated within research-oriented space missions (e.g., CubeSats). In this paper, a run-time reconfigurable implementation of a low-complexity lossless hyperspectral compressor (i.e., CCSDS 123) on a commercial off-the-shelf device is presented. The proposed approach leverages an FPGA-based on-board processing architecture with a data-parallel execution model to transparently manage a configurable number of resource-efficient hardware cores, dynamically adapting both throughput and energy efficiency. The experimental results show that this solution is competitive when compared with the current state-of-theart hyperspectral compressors and that the impact of the parallelization scheme on the compression rate is acceptable when considering the improvements in terms of performance and energy consumption. Moreover, scalability tests prove that run-time adaptation of the compression throughput and energy efficiency can be achieved by modifying the number of hardware accelerators, a feature that can be useful in space scenarios, where requirements change over time (e.g., communication bandwidth or power budget). INDEX TERMS Data compression, dynamic and partial reconfiguration, FPGAs, high-performance embedded computing, hyperspectral images, on-board processing.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

et al. 2019

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“…The comparison of the proposed parallel implementation of CCSDS-123 algorithm with recent sequential [12][13][14][15]17,18] and parallel [16] FPGA implementations with regards to maximum frequency, the throughput performance and power is presented in Table 4. The majority of implementations target Virtex-5 FX130T FPGA which is commercial equivalent of radiation hardened Virtex-5QV.…”

Section: Comparison With State-of-the-art Implementationsmentioning

confidence: 99%

“…In particular, the CCSDS-123 compression standard [10,11] is an efficient prediction-based algorithm characterized by low complexity and, thus, is suitable for real-time hardware implementation. In fact, in the recent years several FPGA implementations of the CCSDS-123 standard are presented in the literature [12][13][14][15][16][17][18][19]. Keymeulen et al [12] propose an on-the-fly implementation in BIP sample ordering.…”

Section: Introductionmentioning

confidence: 99%

A Parallel FPGA Implementation of the CCSDS-123 Compression Algorithm

2019

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Satellite onboard processing for hyperspectral imaging applications is characterized by large data sets, limited processing resources and limited bandwidth of communication links. The CCSDS-123 algorithm is a specialized compression standard assembled for space-related applications. In this paper, a parallel FPGA implementation of CCSDS-123 compression algorithm is presented. The proposed design can compress any number of samples in parallel allowed by resource and I/O bandwidth constraints. The CCSDS-123 processing core has been placed on Zynq-7035 SoC and verified against the existing reference software. The estimated power use scales approximately linearly with the number of samples processed in parallel. Finally, the proposed implementation outperforms the state-of-the-art implementations in terms of both throughput and power.

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“…Very recently, the CCSDS has superseded Issue 1 of the Lossless Multispectral & Hyperspectral Image Compression standard [7] with Issue 2 titled Low-Complexity Lossless and Near-Lossless Multispectral and Hyperspectral Image Compression (CCSDS-123.0-B-2) [8]. The original issue of the standard employed the fast lossless compression algorithm [9,10] to achieve state-of-the-art compression performance, whilst being implemented in resource-constrained hardware available for space operation [11][12][13][14][15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

Performance Impact of Parameter Tuning on the CCSDS-123.0-B-2 Low-Complexity Lossless and Near-Lossless Multispectral and Hyperspectral Image Compression Standard

et al. 2019

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This article studies the performance impact related to different parameter choices for the new CCSDS-123.0-B-2 Low-Complexity Lossless and Near-Lossless Multispectral and Hyperspectral Image Compression standard. This standard supersedes CCSDS-123.0-B-1 and extends it by incorporating a new near-lossless compression capability, as well as other new features. This article studies the coding performance impact of different choices for the principal parameters of the new extensions, in addition to reviewing related parameter choices for existing features. Experimental results include data from 16 different instruments with varying detector types, image dimensions, number of spectral bands, bit depth, level of noise, level of calibration, and other image characteristics. Guidelines are provided on how to adjust the parameters in relation to their coding performance impact.

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A 3.3 Gbps CCSDS 123.0-B-1 Multispectral & Hyperspectral Image Compression Hardware Accelerator on a Space-Grade SRAM FPGA

Cited by 32 publications

References 7 publications

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

A Parallel FPGA Implementation of the CCSDS-123 Compression Algorithm

Performance Impact of Parameter Tuning on the CCSDS-123.0-B-2 Low-Complexity Lossless and Near-Lossless Multispectral and Hyperspectral Image Compression Standard

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