A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR

Pan, Hui; Segami, M.; Choi, Michael; Cao, Jing; Hatori, F.; Abidi, A.A.

doi:10.1109/4.890290

Cited by 85 publications

(4 citation statements)

References 55 publications

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“…The value of the spurious-free dynamic rang (SFDR) is 75dB as well. The power consumption of this ADC shows more than 2X reduction in power consumption compared to recentlyreported 12-bit ADCs [10][11][12][13]. …”

Section: Design Examplementioning

confidence: 98%

Systematic design for power minimization of pipelined analog-to-digital converters

Lotfi¹,

Teherzadeh-Sani²,

Azizi³

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total power consumption and the total input-referred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, an optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specific noise requirement is satisfied. To determine the bias current values of operational amplifiers an optimal choice for settling and slewing time parameters is proposed. A practical design example is presented to show the effectiveness of the proposed methodology.

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Section: Design Examplementioning

confidence: 98%

Systematic design for power minimization of pipelined analog-to-digital converters

Lotfi¹,

Teherzadeh-Sani²,

Azizi³

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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“…In order to reduce the impact of aperture errors, the size of the sampling switches in MDACs and sub-ADCs are adjusted to keep the same time constant with different size of sampling capacitors. All these switches are also designed with bootstrapped architecture to improve the linearity [16].…”

Section: Adc Core Designmentioning

confidence: 99%

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

Chen¹,

Shen³

et al. 2019

IEICE Electron. Express

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In this paper, a 14 bit 500 MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) realized in 40 nm CMOS technology is presented. A 2.5 V powered buffer that exhibits a comprehensive bootstrap architecture is proposed to achieve the trade-off between linearity and power consumption. Besides, the high-voltage-thin-oxide-device design is incorporated to further improve the linearity. In the meantime, an improved supply voltage domain arrangement is proposed to achieve a single power design and improve structural power efficiency. The measured Signal-to-Noise-and-Distortion-Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) are 71 dB and 79 dBc at 120.2 MHz input signal under 500 MS/s. The ADC occupies an active area of 0.4 mm 2 and consumes a total power of 300 mW.

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“…As an important modulator, SDM will inevitably play a decisive role affecting the performance of the system. Integrator gain error is mainly caused by capacitor mismatch, finite gain and limited unit-gain bandwidth of operational amplifier, which limits the linearity and resolution of the modulator [3].…”

Section: Introductionmentioning

confidence: 99%

A Noise-Optimal Integrator for High-Precision SC Sigma Delta Modulators

Wang

Zhang

2014

AMM

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Based on N-well Chartered 0.35-um CMOS technology, we designed an integrator for a low-power and high-precision sigma-delta modulator, which has a structure of third-order CIFF, one bit quantization. Amplifier designed in this paper use the PMOS folded cascade differential structure. All switches of the switch capacitance integrator are CMOS switch. The structure-improved integrator can be used to preliminarily filter the noise power of the input signal, and reduce the noise into the modulator, combined with bottom plate sampling technology and the right timing sequence. Input sinusoidal signal has frequency of 65.625Hz and amplitude of 0.6V. It’s simulated in cadence spectre with sampling frequency of 76.8kHz and power supply voltage of 3.3V. FFT analysis of the integrator output shows that the noise floor is-94.3dB, which meets the performance requirements of the system.

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A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR

Cited by 85 publications

References 55 publications

Systematic design for power minimization of pipelined analog-to-digital converters

Systematic design for power minimization of pipelined analog-to-digital converters

A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS

A Noise-Optimal Integrator for High-Precision SC Sigma Delta Modulators

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