A 3.3 V-only 16 Mb DINOR flash memory

Kobayashi, S.; Mihara, M.; Miyawaki, Y.; Ishii, M.; Futatsuya, T.; Hosogane, A.; Ohba, A.; Terada, Yasushi; Ajika, N.; Kunori, Yuichi; Yuzuriha, K.; Hatanaka, M.; Miyoshi, Hirokazu; Yoshihara, Tsutomu; Uji, Y.; Matsuo, A.; Taniguchi, Yukinori; Kiguchi, Y.

doi:10.1109/isscc.1995.535457

Cited by 26 publications

(2 citation statements)

References 3 publications

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“…9(b)], and is the clock period. After evaluating , we can modify the -realm equations as follows: (7) where is the selection vector,…”

Section: Optimized Power Transfer Considerationsmentioning

confidence: 99%

“…While charge boosting is performed at frequencies within 10-30 MHz depending on the desired load current, the frequency should be reduced to less than 100 kHz when operating in a standby mode in order to save the energy. A complete study of the switching frequency in relation to the load requirements was presented in [7]. Frequency regulation should be also related to transistor sizing for efficient transfer of energy from the source to the load.…”

Section: Power Timing and Frequency Considerationsmentioning

confidence: 99%

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A DC-DC charge pump design based on voltage doublers

Starzyk

Jan

Qiu³

2001

IEEE Trans. Circuits Syst. I

221

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A novel organization of switched capacitor charge pump circuits based on voltage doubler structures is presented in this paper. Each voltage doubler takes a dc input and outputs a doubled dc voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler (MPVD) structures are discussed and design considerations are presented. A simulator working in the -realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. A comparison of the voltage doubler circuits with Dickson charge pump and Makowski's voltage multiplier is presented in terms of the area requirements, the voltage gain, and the power level. This paper also identifies optimum loading conditions for different configurations of the charge pumps. Design guidelines for the desired voltage and power levels are discussed. A two-stage MPVD was fabricated using MOSIS 2.0-m CMOS technology. It was designed with internal frequency regulation to reduce power consumption under no load condition.

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“…9(b)], and is the clock period. After evaluating , we can modify the -realm equations as follows: (7) where is the selection vector,…”

Section: Optimized Power Transfer Considerationsmentioning

confidence: 99%

Section: Power Timing and Frequency Considerationsmentioning

confidence: 99%