A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS

Abstract

This paper presents a 14-bit 125MS/s pipeline analog-todigital (ADC) which can be used for communication systems, especially in radar and navigation fields. A high-speed sample-and-hold amplifier (SHA) with a high-linearity bootstrapped switch has been integrated into the ADC to remove the aperture error. To improve the gain bandwidth product of amplifiers, a hybrid 1.8V/3.3V MOSFET technique is proposed, wherein 1.8V MOSFETs are used together with 3.3V devices under a 3.3V supply to utilize the higher intrinsic frequency of the 1.8V MOSFET. Meanwhile, a special bias circuit is designed to guarantee the voltage of each terminal pair of 1.8V devices will not exceed its limit value. The ADC is implemented in 0.18μm 1.8V/3.3V CMOS technology and achieves 72.1dB signal-to-noise ratio (SNR) and 92.6dB spur-free dynamic range (SFDR) with 10.1MHz sine input under 3.3V supply, while consuming 272mW power at 125MS/s. The results show that the ADC is suitable for applications where high-speed and high-resolution devices are required.