A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS

Chang, Chih-Hsiung; Yang, Ching-Yuan; Yu, Liang; Weng, Jun-Hong; Cheng, Nai-Chen Daniel

doi:10.1109/esscirc.2013.6649070

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Power Reduction Techniques1

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2020

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“…In some case, if the divider operation frequency is not so high that it can operate at lower supply voltage, the current-reuse technique [71,72] can be used to reduce power by stacking the VCO with the high-frequency prescaler and the MMD between the supply and ground, as shown in Fig. 12(d).…”

Section: Power Reduction Techniquesmentioning

confidence: 99%

CMOS analog and mixed-signal phase-locked loops: An overview

Zhang¹

2020

J. Semicond.

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CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

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Section: Power Reduction Techniquesmentioning

confidence: 99%

CMOS analog and mixed-signal phase-locked loops: An overview

Zhang¹

2020

J. Semicond.

View full text Add to dashboard Cite

show abstract

A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS

Cited by 1 publication

References 10 publications

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops: An overview

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