A 3.6 mW 60 GHz Low-Noise Amplifier With 0.6 ns Settling Time for Duty-Cycled Receivers

Morath, Helmuth; Testa, Paolo Valerio; Wagner, Jens; Ellinger, Frank

doi:10.1109/lmwc.2021.3082859

Cited by 17 publications

(6 citation statements)

References 26 publications

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“…The last two points can be addressed by operating the WBAN at mmWave frequencies (30 GHz-300 GHz), e.g. around 60 GHz, as suggested in [4]. In addition to a large amount of available bandwidth, the size of an antenna and other passives used in the transceiver scale inversely with frequency [5]- [11].…”

Section: (B)mentioning

confidence: 99%

Characterization of Embedded and Thinned RF Chips

Yin,

Morath,

Hoyer

et al. 2024

IMAPSource Proceedings

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This work studies the effect of thinning down chips with transmission line structures for flexible embedding technology. Test chips with 90 Ω grounded coplanar waveguide (GCPW) transmission lines have been designed and manufactured to characterize the high-frequency performance before and after embedding in sheet molding compound (SMC), and thinning down from 300 μm to 20 μm. Molding first technology enables single-die or multiple-die thinning with the embedding material while being held in the exact position, where the subsequent fanout copper (Cu) redistribution layer (RDL) structuring realizes the direct contacts to the embedded chip, followed by semiadditive manufacturing of traces. The embedded and thinned chips are characterized by S-parameter measurements in the frequency range from 20 MHz to 65 GHz using a vector network analyzer (VNA). The results show the feasibility of the examined embedding and thinning processes which are suitable for millimeter wave (mmWave) components as shown by the example of a G-CPW transmission line without degrading its RF performance in terms of characteristic impedance and attenuation.

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Section: (B)mentioning

confidence: 99%

Characterization of Embedded and Thinned RF Chips

Yin,

Morath,

Hoyer

et al. 2024

IMAPSource Proceedings

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“…respect to the case of using an EDFA after the PIC. A possible way for approaching the performance obtained with the optically amplified signals through the external EDFA would be by using low-noise RF amplifiers specifically designed for low-power signals [49], [50], or by means of on-chip amplification using hybrid integration techniques [51], [52]. A combination of both approaches could also be employed, in conjunction with design strategies for improving the isolation between the input and output RF ports of the circuit, for the development of monolithic full on-chip integrated MWP filter functionality.…”

Section: Integrated Mwp Filter Operation Without Optical Amplificationmentioning

confidence: 99%

Silicon-on-Insulator Microwave Photonic Filter With Widely Tunable and Reconfigurable Flat-Top Bandpass Functionality

Porzi

Reza

Ghelfi³

et al. 2022

J. Lightwave Technol.

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We report of a silicon photonics (SiP) flat-top bandpass microwave photonic (MWP) filter with large out-of-band power rejection (OBPR) of up to more than 40 dB and exhibiting central frequency tunability over a range as large as 70 GHz, while still guaranteeing a minimum full-span OBPR larger than 25 dB. Furthermore, the RF bandpass transfer function can be widely configured without sacrificing the filter performance. In the present realization, a continuous bandwidth tuning from 5 to 10 GHz (corresponding to a 100% of bandwidth variation) is demonstrated. The operation is based on optical-to-RF mapping the response of a tunable and bandwidth reconfigurable photonic integrated optical filter, realized with a high-order distributed feedback resonator (DFBR) waveguide Bragg grating structure. A high level of functional integration is provided in a compact footprint of less than 2 mm 2 by embedding within the circuit a SiP phase modulator generating the modulation sideband scanning the DFBR filter, and a tunable optical splitter optimizing the MWP filter performance. Possibility of further extending system integration for monolithic on-chip operation is also investigated.

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“…On the other hand, however, analog and RF design remains challenging in this technology and the costs are still very high. We used an established 22 nm FDSOI technology, which also provides good capability for fast and power-efficient digital design and, additionally, is one of the best choices for RF design as demonstrated in several works e.g., [9][10] [11]. Hence, a monolithic integration of the RF frontend and high-speed ADC is feasible in this technology and, thus, probably better suited for the latter application.…”

mentioning

confidence: 99%

A 2.5 GS/s, 7-bit time-interleaved SAR ADC with real-time data output

Matthus

Buhr

Ellinger

2023

Preprint

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This letter presents the design and measurement results of a 2.5 GS/s 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) with real-time data output via the JESD204B protocol using two lanes at 12.5 Gb/s each. The ADC is implemented in a 22-nm fully-depleted silicon-on-insulator (FDSOI) technology and consists of four time interleaved ADC cores. It consumes 43 mW overall, while the analog frontend including the four ADC cores and the interleaver consumes only 7.8 mW. In the first Nyquist zone, the effective number of bits (ENOB) is larger than 6.1 bit leading to a Walden Figure-of-Merit (FOM_W) of 45 fJ/conv.-step and a Schreier Figure-of-Merit (FOM_S) of 150.5 dB. Integral (INL) and differential nonlinearity (DNL) are both well below 0.5 LSB for all measurement scenarios.

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A 3.6 mW 60 GHz Low-Noise Amplifier With 0.6 ns Settling Time for Duty-Cycled Receivers

Cited by 17 publications

References 26 publications

Characterization of Embedded and Thinned RF Chips

Characterization of Embedded and Thinned RF Chips

Silicon-on-Insulator Microwave Photonic Filter With Widely Tunable and Reconfigurable Flat-Top Bandpass Functionality

A 2.5 GS/s, 7-bit time-interleaved SAR ADC with real-time data output

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