A 3.8-<i>µ</i>W 1.5-NEF 15-GΩ Total Input Impedance Chopper Stabilized Amplifier With Auto-Calibrated Dual Positive Feedback in 110-nm CMOS

Park, Yongjae; Cha, Ji-Hyoung; Han, Su-Hyun; Park, Jee Ho; Kim, Seong-Jin

doi:10.1109/jssc.2021.3137509

Cited by 20 publications

(4 citation statements)

References 37 publications

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“…[103] Leveraging a dual feedback loop PFL in combination with self-calibration enhances the input impedance to 15 GΩ@10 Hz at 0.75 mm 2 area and 3.63 μA current. [104] Considering that the input impedance of implantable high-density electrodes approximates 100 kΩ@10 kHz, [105,106] IIP exceeds 10 MΩ@10 kHz and is sufficient to prevent over 1% signal attenuation. However, the electrode impedance might reach 1 MΩ during a long recording, necessitating a reliable input impedance boosting technique.…”

Section: Input Impedance Boostingmentioning

confidence: 99%

“…With the help of self‐calibration, PFL allows for an impressive 2.67 GΩ input impedance with 0.405 mm 2 silicon area and 2.8 μA current cost [103] . Leveraging a dual feedback loop PFL in combination with self‐calibration enhances the input impedance to 15 GΩ@10 Hz at 0.75 mm 2 area and 3.63 μA current [104] . Considering that the input impedance of implantable high‐density electrodes approximates 100 kΩ@10 kHz, [105,106] IIP exceeds 10 MΩ@10 kHz and is sufficient to prevent over 1% signal attenuation.…”

Section: High‐density Neural Recording Chipsmentioning

confidence: 99%

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High‐density implantable neural electrodes and chips for massive neural recordings

Wang,

Suo,

Wang

et al. 2024

Brain-X

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High‐density neural recordings with superior spatiotemporal resolution powerfully unveil cellular‐scale neural communication, showing great promise in neural science, translational medicine, and clinical applications. To achieve such, many design and fabrication innovations enhanced the electrode, chip, or both for biocompatibility improvement, electrical performance upgrade, and size miniaturization, offering several thousands of recording sites. However, an enormous gap exists along the trajectory toward billions of recording sites for brain scale resolution, posing many more design challenges. This review tries to find possible insight into mitigating the gap by discussing the latest progress in high‐density electrodes and chips for neural recordings. It emphasizes the design, fabrication, bonding techniques, and in vivo performance optimization of high‐density electrodes. It discusses the promising opportunities for circuit‐level and architecture‐level multi‐channel chip design innovations. We expect that joint effort and close collaboration between high‐density electrodes and chips will pave the way to high‐resolution neural recording tools supporting cutting‐edge neuroscience discoveries and applications.

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Section: Input Impedance Boostingmentioning

confidence: 99%

Section: High‐density Neural Recording Chipsmentioning

confidence: 99%

High‐density implantable neural electrodes and chips for massive neural recordings

Wang,

Suo,

Wang

et al. 2024

Brain-X

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“…With the booming of the biomedical industry, wearable biomedical devices have recently attracted wide attention [1][2][3]. Physiological signal acquisition chips based on the CMOS process are one of the important building blocks of wearable devices [1,4], whose design must meet a series of specification requirements for both analog and digital circuits. Analog front-end (AFE) circuits play an important role in the acquisition of physiological signals and must be designed compatible with the properties of physiological signals [5] that have low-level amplitudes (from tens of µV to tens of mV) and appear mostly in different low-frequency ranges (from sub-Hz to several hundred Hz) [6].…”

Section: Introductionmentioning

confidence: 99%

A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor

Xu,

Liu,

Duan

et al. 2024

Electronics

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Analog front-end (AFE) circuits play an important role in the acquisition of physiological signals with low-level amplitudes (from tens of μV to tens of mV) and broadband low-frequency ranges (from sub-Hz to several hundred Hz). Possessing a high input impedance, an instrumentation amplifier (IA) accurately amplifies signals with low amplitude and low frequency, making it suitable for AFE circuits. This work demonstrates a capacitively coupled IA whose feedback resistance is realized by the proposed hybrid resistor, consisting of a switched-capacitor low-pass filter, a switched-capacitor resistor, and a continuous-time low-pass filter. The capacitively coupled IA achieves tera-ohm (TΩ) resistance and is insensitive to process, voltage, and temperature (PVT) variations. The simulation results show that the proposed IA illustrates a high-pass corner of 73.9 mHz, and the change of its high-pass corner with temperature is 0.05 mHz/°C. With the variation in the PVT corners, the difference between the maximum and minimum values of the high-pass corner of the proposed capacitively coupled IA is only 0.06 Hz. The design was implemented in a 130 nm standard CMOS process. The AFE with the proposed capacitively coupled IA achieves a 53.9 dB signal-to-noise and distortion ratio (SNDR) and 69.5 dB total harmonic distortion (THD).

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“…Because CMOS technology has the advantages of low cost, low power consumption, high integration and high performance [1][2][3][4][5], and with the further development of CMOS technology to deep submicron, the feature size of the device is gradually reduced, and the feature frequency is further increased, so it is possible to design high-speed integrated circuit with CMOS technology. The sample and hold (S/H) circuit is also called sample and hold amplifier.…”

Section: Introductionmentioning

confidence: 99%

A 1 V, 10 KS/S, 71.2 db SNDR current-mode CMOS sample-and-hold circuit for high-speed wireless communication applications

Gao

Cai

et al. 2022

Preprint

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The sample and hold circuit has the function of collecting the analog input signal at a moment and maintaining its value. This article presents a current-mode sample and hold circuit for high-speed wireless communication applications. In this circuit, a single amplifier and a negative feedback structure are combined to eliminate the clock-feed through noise by using a virtual switch, and a differential structure is used to reduce the distortion caused by channel charge injection. This architecture achieves 71.2 db SNDR (signal to noise ratio plus distortion ratio) with a sampling rate of 10 KS/S when the power supply voltage is 1 V. The design of the sample and hold circuit is verified by the post-layout simulation of the standard 0.18 um CMOS technology.

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A 3.8-µW 1.5-NEF 15-GΩ Total Input Impedance Chopper Stabilized Amplifier With Auto-Calibrated Dual Positive Feedback in 110-nm CMOS

Cited by 20 publications

References 37 publications

High‐density implantable neural electrodes and chips for massive neural recordings

High‐density implantable neural electrodes and chips for massive neural recordings

A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor

A 1 V, 10 KS/S, 71.2 db SNDR current-mode CMOS sample-and-hold circuit for high-speed wireless communication applications

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