A 300 MHz 115 W 32 b bipolar ECL microprocessor with on-chip caches

Abstract

A full-custom 32b ECL microprocessor uses a l.0pm-drawn single-poly technology with four layers of aluminum and one layer of gold interconnect. The 15.4x12.6mm2 die contains 468k bipolar transistors (ft=13GHz) and 206kresistors. Figure 1 shows the chip before gold metalization and gives the floor plan. A breakdown of transistor and area usage is given in Table 1. The chip implements a subset of an existing RISC architecture [21. Hardware support for floating-point arithmetic and virtual memory is not implemented on this chip.Worst-case power dissipation with a -5.2V supply is 115W. One-mil-thick gold bus bars covering the entire chip distribute the 26A supply current (Figure 2). The low resistance of the gold bus bars is the major factor in meeting a 15mV total IR drop on each supply. The chip has 202 ECL lOOk inputs, 157 ECL lookoutputs, and254power pads. Theinnerrow ofpower pads is bonded with 1.8mil gold wires, and signals in the outer row are bonded with 1.25mil gold wires. All input pads include 50C2 terminations to a -2V supply. The chip is packaged in a 504-pin plastic PGA with decoupling capacitors in the die cavity. The chip is attached with low-modulus epoxy to a copper spreader forming the boiling surface for a thermosiphon (a heatpipe without a wick) giving a typical average junction temperature of 100°C [lJ. In normal operation, there is a temperature gradient of 25°C across the die. Figure 3 shows the package and thermosiphon.Worst-case clock frequency is 275MHz a t nominal -5.2V supply. Operation is in excess of 335MHz with a -3.9V supply.The machine has 5 pipeline stages, each one clock cycle long ( Figure 4). In instruction fetch (IF), the PC is sent to the 2kB instruction cache and the instruction at that address is read, cache tags are compared, instruction parity is checked, and the instruction is decoded. In the RD pipestage the source operands are read from the register file. 32b integer addition, subtraction, logical and shift operations, and addressing calculations take place in the ALU pipestage. In the MEM pipestage the 2kB on-chip write-through data cache is read or written. Instruction results are written to the register file and store instructions place their result in the write buffer for transfer to the external cache in the WB pipestage.A 128b bus is used for incoming data. A 64b bus Is used for outgoing data. All external data busses have byte parity. Separate address busses of 32b and 14b are used to index the external cache data and tags, respectively. Two unidirectional l l b busses are used to read and write second-level cache tags.Scan data is input on a n 8b bus and output on another 8b bus.The chip uses a single-phase differential clock. A PLL generates a l x to 8x multiple of an off-chip differential clock for use on-chip. All communication between the chip and board is synchronous. A typical external clock frequency is 80MHz. All on-chip non-RAM state devices are flip-flops with scan. U 0 pads have flip-flops clocked by the board clock. The PLL has circuitry generating s...

Physical performance limits for shared buffer ATM switches

“…If we can characterize internal dynamic power dissipation of the switch chip according to (18), we can determine a figure of merit for each switch implementation, given by (26) This value is calculated for each of our five sample switches, and the results are shown in Table III.…”

“…Successful implementations will require careful power management to achieve a low value for , and to dissipate heat efficiently. We estimate total power dissipation, including optical I/O, for the 1.3 Tb/s 0.25 m single-chip switch to be 156 W. An example of dealing with this order of power dissipation is the "thermosiphon" attached to a 115 W microprocessor in [26]. Supply current could be routed by a gold bus bar arrangement similar to that used in [26].…”

An ECL gate with improved speed and low power in BiCMOS process

“…This assures that the transistors Q1 and Q2 are driven in opposite phases thus eliminating direct current path from Vcc to Low to High transition of the output stage is achieved by driving Q1. The output node will assume high value and after a set delay through the feedback path (4) it will enable a current path in the current mirror of the controlled current source (2). However, it will not result in high current because the input from the logic stage (1) will keep the controlled current source in the low current mode.…”

“…The transistor Q2 will be driven by a high current from the current mirror thus resulting in a fast transition from high to Zow at the output. After this transition the output value low will be passed with same delay in the feedback stage (4) to the controlled current source (2). The path of the current mirror will be disconnected, thus reducing the current driving Q2.…”