A 32-bit SoPC implementation of a P/sup 5/

Toal, C.; Sezer, Sakir

doi:10.1109/iscc.2003.1214168

Cited by 5 publications

(2 citation statements)

References 2 publications

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“…The use of SoPC designs varies from digital drive controllers [1,2] and general SoPC implementations for supporting student projects [3,4] to programmable protocol processors [5] and controllers for robotic applications [6]. Moreover because of FPGAs being reconfigurable in nature, functions can be implemented directly in hardware, reducing computational time [7,8].…”

Section: Introductionmentioning

confidence: 99%

Area efficient system-on-programmable-chip design for a wireless touch-triggered machining probe

Mimis

Koçak

2011

2011 6th IEEE Conference on Industrial Electronics and Applications

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Abstract-In this paper, we present the design and implementation details of a System-on-Programmable-Chip (SoPC), which replaces the circuitry that controls the operation of a touchtriggered machining probe with radio transmission capability. The probe is used to get precise measurements of three dimensional geometric parts. The goal is to achieve size reduction of an existing circuitry inside the probe, that consists of two microcontrollers and a reconfigurable hardware device such as a Field Programmable Gate Array (FPGA), that implements some custom functions. In order to reduce the printed circuit board (PCB) area occupied by these three chips and the associated routing area, we combine them on a single SoPC. An overall 6 fold reduction in PCB area occupied, corresponding to nearly 15cm 2 is achieved.

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Section: Introductionmentioning

confidence: 99%

Area efficient system-on-programmable-chip design for a wireless touch-triggered machining probe

Mimis

Koçak

2011

2011 6th IEEE Conference on Industrial Electronics and Applications

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“…[1], [2] and [3] describe implementations of a processor related to the point-to-point protocol. Research has also been performed related to FPGA based scheduling but MPLS architectures are not prevalent in the literature.…”

Section: Introductionmentioning

confidence: 99%

Embedded MPLS Architecture

Peterkin¹,

Ionescu²

19th IEEE International Parallel and Distributed Processing Symposium

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This paper presents a hardware architecture for Multi Protocol Label Switching (MPLS). MPLS is a protocol used primarily to prioritize internet traffic and improve bandwidth utilization. Furthermore it increases the performance of internet applications and overall efficiency. However, most existing MPLS solutions are entirely software based. MPLS performance can be enhanced by executing core tasks (i.e. label stack modification) in hardware while allowing other tasks to be executed in software to guard against performance degradation. This paper proposes a hardware/software design of MPLS on an FPGA for increased performance and efficiency. Greatest emphasis is placed on the hardware components.

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A 10 Gbps GFP frame delineation circuit with single bit error correction on an FPGA

Toal

Sezer

2005

Advanced Industrial Conference on Telecommunications/Service Assurance With Partial and Intermittent Resources Conference/E-Lea

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A 32-bit SoPC implementation of a P/sup 5/

Cited by 5 publications

References 2 publications

Area efficient system-on-programmable-chip design for a wireless touch-triggered machining probe

Area efficient system-on-programmable-chip design for a wireless touch-triggered machining probe

Embedded MPLS Architecture

A 10 Gbps GFP frame delineation circuit with single bit error correction on an FPGA

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