A 32 GSample/sec SiGe HBT Comparator for Ultra-High-Speed Analog-to-Digital Conversion

Kuo, Wei-Min Lance; Li, Xiangtao; Krithivasan, R.; Lei, Yuan; Cressler, John D.; Borokhovych, Y.; Gustat, H.; Tillack, Bernd; Heinemann, B.

doi:10.1109/apmc.2005.1606245

Cited by 9 publications

(5 citation statements)

References 9 publications

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“…Due to the use of a broadband Cherry-Hooper preamplifier to create a large bandwidth instead of using a traditional differential amplifier, the gain of preamplifier is less than in Ref. [2]. Some sensitivity enhancement techniques have been used in Ref.…”

Section: Measurements and Resultsmentioning

confidence: 99%

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A 20-GHz ultra-high-speed InP DHBT comparator

Zhenxing¹,

Zhou²,

Su³

et al. 2012

J. Semicond.

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An ultra-high-speed, master-slave voltage comparator circuit is designed and fabricated using InP/GaInAs double heterojunction bipolar transistor technology with a current gain cutoff frequency of 170 GHz. The complete chip die, including bondpads, is 0.75 1.04 mm 2 . It consumes 440 mW from a single -4 V power supply, excluding the clock part. 77 DHBTs have been used in the monolithic comparator. A full Nyquist test has been performed up to 20 GHz, with the input sensitivity varying from 6 mV at 10 GHz to 16 mV at 20 GHz. To our knowledge, this is the first InP based integrated circuit including more than 70 DHBTs, and it achieves the highest sampling rate found on the mainland of China.

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Section: Measurements and Resultsmentioning

confidence: 99%

“…The sensitivity of our comparator is fairly good, but inferior to Refs. [2,8] at a similar sampling rate. To the best of our knowledge, the comparator in Ref.…”

Section: Measurements and Resultsmentioning

confidence: 99%

A 20-GHz ultra-high-speed InP DHBT comparator

Zhenxing¹,

Zhou²,

Su³

et al. 2012

J. Semicond.

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“…The increased chip area is due to an 8-channel implementation and the topology of each comparator. The comparators in WenWei and Qiao (2014) and Kuo et al (2005) have improved gain performance and a smaller active area than the current C-H design, but have a smaller bandwidth and output swing. The designs of both are similar utilizing cascaded gain stages, each with high bandwidth to improve the overall gain.…”

Section: Simulation Setup and Resultsmentioning

confidence: 99%

High-speed Cherry Hooper flash analog-to-digital converter

Fauré

Sinha

2017

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Purpose -The 60 GHz unlicensed band is being utilized for high speed wireless networks with data rates in the gigabit range. In order to successfully make use of these high speed signals in a digital system, a high speed analog-to-digital converter (ADC) is required. This paper presents the use of a common collector (CC) input tree and Cherry Hooper differential amplifier to enable analog-to-digital conversion at high frequencies. Approach -The CC input tree is designed to separate the input Miller capacitance of each comparator stage. The CC stages are biased to obtain bandwidth speeds higher than the comparator stages while using less current than the comparator stages. The Cherry Hooper differential amplifier is modified to accommodate the low breakdown voltages of the technology node and used as a comparator. The comparator stages are biased to obtain a high output voltage swing and have a small signal bandwidth up to 29 GHz. Simulations were performed using foundry development kits to verify circuit operation. A two-bit ADC was prototyped in IBM's 130 nm silicon-germanium (SiGe) bipolar complementary metal-oxide-semiconductor (BiCMOS) 8HP technology node. Measurements were carried out on test printed circuit boards (PCBs) and compared with simulation results. Findings -The use of the added CC input tree showed a simulated bandwidth improvement of approximately 3.23 times when compared to a basic flash architecture for a two-bit ADC. Measured results showed an effective number of bits (ENOB) of 1.18, from DC up to 2 GHz, whereas the simulated result was 1.5. The maximum measured integral non-linearity (INL) and differential nonlinearity (DNL) was 0.33 least significant bits (LSBs). The prototype ADC had a figure of merit of 42 pJ/sample. Originality/value -The prototype ADC results showed that the group delay for the Cherry Hooper comparator plays a critical role in ADC performance for high frequency input signals. For minimal component variation the group delay between channels deviate from each other, causing incorrect output codes. The prototype ADC had a low gain which reduced the comparator performance. The two-bit CC Cherry Hooper ADC is capable of achieving an ENOB close to 1.18 for frequencies up to 2 GHz, with 180 mW total power consumption.

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“…The last term is negligible since g m7,8 R C7,8 >>1. The maximum sampling rate of the latch is limited by the recovery time [3] given by:…”

Section: Circuit Designmentioning

confidence: 99%

A 500 °C Monolithic SiC BJT Latched Comparator

Tian

Lanni

Rusu

2016

MSF

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This paper presents a monolithic 4H-SiC BJT latched emitter-coupled logic (ECL) comparator for high temperature analog-to-digital conversion. The comparator consists of a low-gain pre-amplifier, a track and latch stage and an output buffer. For low-speed input signals, the comparator input offset voltage is 3.9 mV at 27 °C and monotonically increases up to 9.1 mV at 500 °C. The single-ended output swing is 5.5 V at 27 °C and 3.9 V at 500 °C. The minimum comparison time is around 1μs from 27 °C to 500 °C. The whole comparator dissipates 464 mW in average over the considered temperature range with a 15 V power supply. It consumes 2.25 × 0.84 mm2 chip area (with the bond pads included).

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A 32 GSample/sec SiGe HBT Comparator for Ultra-High-Speed Analog-to-Digital Conversion

Cited by 9 publications

References 9 publications

A 20-GHz ultra-high-speed InP DHBT comparator

A 20-GHz ultra-high-speed InP DHBT comparator

High-speed Cherry Hooper flash analog-to-digital converter

A 500 °C Monolithic SiC BJT Latched Comparator

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