A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS

Grover, Anuj; Visweswaran, G. S.; Parthasarathy, C.; Daud, Mohammad; Turgis, David; Giraud, B.; Noël, Jean-Philippe; Miro-Panades, Ivan; Moritz, Guillaume; Beigné, Edith; Flatresse, Philippe; Kumar, Promod; Azmi, Shamsi

doi:10.1109/tcsi.2017.2705116

Cited by 15 publications

(4 citation statements)

References 20 publications

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“…This is in addition to the read and hold stability of memory cells, both enhanced by the appropriate cell design. By including assist circuits in the memory design, the write-ability of the device may be improved [9,[11][12][13][14][15][16][17][18][19][20][21][22][23]. The main intention of designing the proposed assist circuit is to improve the write performance.…”

Section: Introductionmentioning

confidence: 99%

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

Ganesh,

Sai Kumar,

Shoukath Vali

et al. 2024

Eng. Res. Express

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This work presents a collapsed supply and boosted bit-line swing (CSBBS) write driver circuit, with the specific goal of enhancing write performance. The write ability of SRAM cells is gravely affected by device parameter variations in deep sub-threshold region of operations. The collapsed supply and boosted bit-line swing are key features aimed at achieving improvements in speed and efficiency during the memory write process. In comparison to conventional, Ultra dynamic scaled supply write (UDSS), Negative charge-boosted bit line (NCBBL), and Reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuits, Proposed collapsed supply and boosted bit-line swing (CSBBS) for 9T SRAM cell has optimized write access delays of 0.74X, 0.41X, 0.32X and 0.21X, improvement in write margin (WM) of 1.51X, 1.34X, 1.22X and 1.12X respectively. The CSBBS Write driver circuit is implemented using custom compiler (Synopsys) through a 28nm BSIM4 model card for bulk CMOS. MC simulation results are monitored on Cosmoscope wave viewer (Synopsys).

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Section: Introductionmentioning

confidence: 99%

A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM

Ganesh,

Sai Kumar,

Shoukath Vali

et al. 2024

Eng. Res. Express

View full text Add to dashboard Cite

show abstract

“…In addition, SRAMs operating in the near-or sub-threshold have significantly degraded Ion-to-Ioff ratios and exponentially increased variations, which deteriorates various SRAM design parameters. Many design techniques have been proposed to partially address these SRAM design issues [40][41][42][43][44][45][46][47][48][49].…”

Section: Introductionmentioning

confidence: 99%

“…On the contrary, lowering cell supply voltage [47,48], word-line overdrive (WLOD), and raising VSS [38] will enhance WM while leading to deteriorated SNM. Another technique is using negative bit-line (NBL) [13,49] for WM enhancement.…”

Section: Introductionmentioning

confidence: 99%