A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Chang, Ik Joon; Kim, Jae‐Joon; Park, S.P.; Roy, Kaushik

doi:10.1109/jssc.2008.2011972

Cited by 399 publications

(214 citation statements)

References 17 publications

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“…3) than the supply voltage of the memory cell arrays in order to attain strong writability, which is similar to the "boosted word line" technique [19], [20]. In this paper, VWRITE was consistently set to VDDL + 0.1 V. VFOOT ( Fig.…”

Section: Sram Structurementioning

confidence: 99%

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Fuketa

Harada

Hashimoto

et al. 2014

IEEE Trans. Device Mater. Relib.

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Abstract-This paper presents measurement results of alphaparticle-induced soft errors and multiple-cell upsets (MCUs) in 65-nm 10T SRAM with a wide range of supply voltage from 1.0 to 0.3 V. We reveal that the soft-error rate (SER) at 0.3 V is six times higher than that at 1.0 V and the MCU rate significantly increases in the subthreshold region. To investigate the reason for the MCU increase, the dependences of the MCU rate on the body-bias voltage and the distance between well ties are examined, and we conclude that the main cause of the MCU increase is not the parasitic bipolar effect but another mechanism, such as charge sharing. In addition, the dependence of the variation in the soft-error immunity of each memory cell on the supply voltage is examined, since SRAMs operating in the subthreshold region are sensitive to manufacturing variability. Measurement results indicate that the number of soft errors in each memory cell varies cell by cell, whereas the cause of the variation is explained by the spatial randomness of alpha-particle hits, and a distinct influence of manufacturing variability is not observed even in the subthreshold region.Index Terms-Alpha-particle-induced soft error, multiple-cell upset (MCU), soft-error rate (SER), subthreshold circuit.

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Section: Sram Structurementioning

confidence: 99%

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Fuketa

Harada

Hashimoto

et al. 2014

IEEE Trans. Device Mater. Relib.

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“…For each type of disrupt event, 1000 MC samples, taking into account both local and global variations, were simulated. Table I presents the SEU tolerance of four bitcells -the standard 6T, the DICE [15], the Quatro-10T [24], and the recently proposed SHIELD cell [23]. Assuming a natural space environment with a charge deposition of 1 pC [25], the results show that the DICE and SHIELD circuits are both suitable candidates, while the 6T and Quatro-10T cells do not provide sufficient immunity.…”

Section: Seu Immunity Comparisonmentioning

confidence: 99%

Single event upset mitigation in low power SRAM design

Atias

Teman

Fish

2014

2014 IEEE 28th Convention of Electrical &Amp; Electronics Engineers in Israel (IEEEI)

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Abstract-Technology advancements in recent years have led to an increase in the employment of integrated circuits in space applications. However, these applications operate in a highly radiated environment, causing a high probability of single event upsets (SEU). Continuous transistor scaling exacerbates the situation, as susceptibility to SEUs is increased in advanced process technologies. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Accordingly, maintaining data integrity in light of SEUs has become an integral aspect of memory cell design. This paper introduces recently proposed methods for mitigating SEUs, and reviews the advantages and disadvantages of leading memory radiation hardening solutions. A brief comparison of radiation hardened bitcells is provided, based on Monte Carlo simulations in a 65 nm CMOS process under slightly scaled supply voltages.

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“…In sub-threshold operation, the conventional 6T SRAM suffers from poor read stability and weak writability [4,5]. We need to note that in 6T SRAM the read stability and the writability may have conflicting design (e.g.…”

Section: Introductionmentioning

confidence: 99%

Subthreshold 8T SRAM sizing utilizing short-channel V<sub>t</sub> roll-off and inverse narrow-width effect

Chang

Yang

2016

IEICE Electron. Express

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8T SRAM have been considered for robust subthreshold SRAM design. Their subthreshold operation was successfully demonstrated through real silicon measurements. However, Monte-Carlo simulation results show that this SRAM still may not deliver sufficient reliability in subthreshold operation. In this work, we overcome this problem by properly sizing SRAM transistors. We utilize short-channel V t roll-off and inverse narrow-width effect for the sizing. Since minimum geometry transistors are employed in the SRAM bit-cell, these effects can have profound impact on SRAM stability. Hence, the proposed approach provides an efficient way to increase the yield of the 8T subthreshold SRAMs.

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A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Cited by 399 publications

References 17 publications

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Single event upset mitigation in low power SRAM design

Subthreshold 8T SRAM sizing utilizing short-channel V<sub>t</sub> roll-off and inverse narrow-width effect

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