A 320 MFLOPS CMOS floating-point processing unit for superscalar processors

Ide, N.; Fukuhisa, H.; Kondo, Y.; Yoshida, Toshiya; Nagamatsu, M.; Junji, M.; Yamazaki, Isamu; Ueno, Katsunori

doi:10.1109/4.210003

Search citation statements

Order By: Relevance

Paper Sections

Select...

Combination Of Single-rail and Dual-rail Circuits1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

1994

2004

Publication Types

Select...

Article3

Book2

Other1

Relationship

Self Cite1

Independent5

Authors

Journals

Cited by 15 publications

(1 citation statement)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This calculation time of 16Ons is almost the same as other synchronous implementation using 0.5 ,U m CMOS technology [7]. In our previous work [3], the zerooverhead scheme also showed a very fast calculation, 2.5 times as fast as the synchronous implementation in a shared division and square root unit.…”

Section: Combination Of Single-rail and Dual-rail Circuitsmentioning

confidence: 75%

A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuit

Matsubara

Ide²

Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems

Self Cite

View full text Add to dashboard Cite

An asynchronous pipeline scheme that combines a low power static circuit with a high-speed dual-rail dynamic circuit is proposed. The scheme utilizes a dual-rail circuit only in the critical path of an SRT division and square root calculation unit. The proposed implementation of the calculation unit reduced power consumption by more than 112 of the full-dynamic implementation while maintaining the calculation speed. Because of the elimination of spurious transitions, the proposed implementation showed even less power consumption over synchronous static circuit implementations. By using 0.3 , U m triple metal CMOS technology, the calculation time of floating point 56-b full mantissa division and square root is expected to be 45ns in the worst case.

show abstract

Section: Combination Of Single-rail and Dual-rail Circuitsmentioning

confidence: 75%