ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
DOI: 10.1109/isscc.2005.1494068
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A 322MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

Iida Iida1,
Kuroda Kuroda2,
Otsuka Otsuka3
et al.
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A 1.8-ns random cycle SRAM-interface High-speed DRAM (SH-RAM) compiler with Data Line Replica Architecture

Kuroda
1
,
Yamada
2
,
Nakamura
3
et al. 2008
2008 IEEE Asian Solid-State Circuits Conference
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A 1.8-ns random cycle SRAM-interface High-speed DRAM (SH-RAM) compiler with Data Line Replica Architecture

Kuroda
1
,
Yamada
2
,
Nakamura
3
et al. 2008
2008 IEEE Asian Solid-State Circuits Conference
0
0
0
0
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A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI

Arimoto
1
,
Morishita
2
,
Hayashi
3
et al. 2006
IEEE Custom Integrated Circuits Conference 2006
1
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0
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Low-voltage embedded RAMs in the nanometer era

Itoh
1
2005
2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.
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