A 32Gb MLC NAND flash memory with V&lt;inf&gt;th&lt;/inf&gt; margin-expanding schemes in 26nm CMOS

Kim, Tae-yun; Lee, Sang−Don; Park, Jin-Su; Cho, Ho-youb; You, Byoung-Sung; Baek, Kwang-Ho; Lee, Jae-Ho; Yang, Chang-won; Yun, Miyong; Kim, Minsu; Kim, Jong-woo; Jang, Eun-seong; Chung, Hyun Kyu; Lim, Sang-o; Han, Bong-Seok; Koh, Young Jun

doi:10.1109/isscc.2011.5746282

Cited by 9 publications

(4 citation statements)

References 4 publications

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“…Since the measured threshold voltage distributions of recent flash memory products [2][3][4] are unimodal, the proposed verify level control criteria can be effectively applied to flash memories. In addition, the proposed verify level control criteria can be applied to other memories such as phase change memory (PCM) because the measured distributions of PCM in literature seem to be unimodal [26][27][28].…”

Section: Verify Level Control Criteria and Other Statistical Distribumentioning

confidence: 99%

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Verify level control criteria for multi-level cell flash memories and their applications

Kim

Kong

et al. 2012

EURASIP J. Adv. Signal Process.

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In M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2 M states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2 M states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell.

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Section: Verify Level Control Criteria and Other Statistical Distribumentioning

confidence: 99%

“…To satisfy the market demand for lower cost per bit and higher density of nonvolatile memory, there are two approaches: (1) technology scaling, (2) multi-level cell (MLC) [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Verify level control criteria for multi-level cell flash memories and their applications

Kim

Kong

et al. 2012

EURASIP J. Adv. Signal Process.

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“…There are a variety of non-volatile memory (NVM) devices established previously that can be generally grouped according to their memory operation principles [1]. The actual mainstream for NVM devices is FLASH technology with other emerging technologies including resistive RAM (R-RAM), magnetic RAM (M-RAM) and phase-change RAM (PCRAM) [2][3][4][5]. These NVM technologies use different types of data storage mechanisms to preserve the information, for example a charge retention layer for FLASH, tunable conductivity material in R-RAM, spin memorization material for M-RAM, and tunable phase change material in PCRAM.…”

Section: Introductionmentioning

confidence: 99%

Anchor-free NEMS non-volatile memory cell for harsh environment data storage

Singh

Chua

Liang

et al. 2014

J. Micromech. Microeng.

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This work demonstrates a novel anchor-free nano-electromechanical (NEMS) based nonvolatile memory cell, suitable for high temperature (T ≤ 300 °C) and radiation prone harsh environment applications. The anchor-free circular metal beam is actuated by electrostatic force and is held in one of the bi-stable memory states by adhesion force between two smooth metal surfaces in contact. Smooth metal layers form strong van der Waals stiction between two surfaces in contact and memory detection (Logic-'1' / Logic-'0') is obtained by detecting the conductance between two fixed contacts. This anchor-free design offers highest density (9F 2 footprint) compared to other mechanical memory devices reported to date.

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“…1. The mainstream solution for NVM integration is FLASH technology [11], [12]. Emerging NVMs typically include resistive RAMs (R-RAM) [13], magnetic RAMs (M-RAM) [14], phase-change RAMs (PC-RAM) [15], conductive-bridge RAMs (CB-RAM) [16], and ferroelectric RAMs (Fe-RAM) [17].…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of anchorless shuttle nano-electro-mechanical non-volatile memory for high temperature applications

Vaddi

Kim

Pott

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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A 32Gb MLC NAND flash memory with V<inf>th</inf> margin-expanding schemes in 26nm CMOS

Cited by 9 publications

References 4 publications

Verify level control criteria for multi-level cell flash memories and their applications

Verify level control criteria for multi-level cell flash memories and their applications

Anchor-free NEMS non-volatile memory cell for harsh environment data storage

Design and analysis of anchorless shuttle nano-electro-mechanical non-volatile memory for high temperature applications

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