A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

Chang, Ik Joon; Kim, Jae‐Joon; Park, S.P.; Roy, Kaushik

doi:10.1109/isscc.2008.4523220

Cited by 87 publications

(52 citation statements)

References 3 publications

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“…Recently, a number of works [1][2][3][4] have shown aggressive supply voltage reduction to near or below the threshold voltage (Vth) of MOSFET devices with considerable reduction in power consumption. However, this power improvement has come at the cost of operation speed (typically <10 MHz).…”

Section: Introductionmentioning

confidence: 99%

Low power circuit design based on heterojunction tunneling transistors (HETTs)

Kim

Lee

Cai

et al. 2009

Proceedings of the 2009 ACM/IEEE International Symposium on Low Power Electronics and Design

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The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low supply voltages. This paper investigates extremely-low power circuits based on new Si/SiGe HEterojunction Tunneling Transistors (HETTs) that have subthreshold swing < 60 mV/decade. Device characteristics as determined through Technology Computer Aided Design (TCAD) tools are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that a HETT-based ring oscillator (RO) shows a 9−19X reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional MOSFETs, namely asymmetric current flow and increased Miller capacitance, analyzing their effect on circuit behavior and proposing methods to address them. Finally, HETT characteristics have the most dramatic impact on SRAM operation and hence we propose a novel 7-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7−37X reduction in leakage power compared to CMOS.

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Section: Introductionmentioning

confidence: 99%

Low power circuit design based on heterojunction tunneling transistors (HETTs)

Kim

Lee

Cai

et al. 2009

Proceedings of the 2009 ACM/IEEE International Symposium on Low Power Electronics and Design

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“…Fig. 3 plots the change in power consumption of low-power LSI chips reported from 2007 to 2014 at ISSCC and VLSI Circuits [3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37], which are the most popular international conferences in the semiconductor industry. It is found that there are three domains: milliwatt, microwatt, and nanowatt.…”

Section: Trends In Circuit Technology and Energy Harvestingmentioning

confidence: 99%

Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting

Morimura¹,

Oshima²,

Matsunaga³

et al. 2014

IEICE Electron. Express

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This paper describes circuit techniques for energy-harvesting technology in millimeter-size ultra-low-power batteryless wireless sensor nodes as a front end for BigData, IoT, M2M, and ambient intelligence. Power generated by energy harvester becomes as small as the nanowatt level when the size of a sensor node becomes millimeter-size. First, technical trends in low-power circuits and the portfolio of energy harvesting and circuit technology are discussed from the viewpoints of technical and application issues. Then, circuit techniques for nanowatt level wireless sensor nodes -a zero-power vibration sensing circuit, power management with MEMS switch, and an intermitted RF transmitter -are explained.

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“…Thus many works have been carried out on the subthreshold operation of logic circuits 3)-7) and SRAM's 8) , where V DD is less than V TH of transistors. However, the number of transistors of the previously reported subthreshold circuits is small (e.g., 70 k transistor logic circuits at V DD of 230 mV 3) , a 32 kbit SRAM at V DD of 160 mV 8) , and a 1000 stage inverter chain at V DD of 60 mV 6) ), and the possibility of the mega gate scale subthreshold circuits is not clear.…”

Section: Fine-grain Body Bias Control To Reduce V Ddminmentioning

confidence: 99%

Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

Takamiya

Sakurai

2009

IPSJ Transactions on System LSI Design Methodology

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In order to cope with the increasing leakage power and the increasing device variability in VLSI's, the required control size of both the space-domain and the time-domain is decreasing. This paper shows the several recent fine-grain voltage engineerings for the low power VLSI circuit design. The space-domain fine-grain voltage engineering includes the fine-grain power supply voltage with 3D-structured on-chip buck converters with the maximum power efficiency up to 71.3% in 0.35-µm CMOS and the fine-grain body bias control to reduce power supply voltage in 90-nm CMOS. The time-domain fine-grain voltage engineering includes accelerators for the power supply voltage hopping with a 5-ns transition time in 0.18-µm CMOS, the power supply noise canceller with the 32% power supply noise reduction in 90-nm CMOS, and backgate bias accelerators for fast wake-up with 1.5-V change of backgate voltage in 35 ns in 90-nm CMOS.

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A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

Cited by 87 publications

References 3 publications

Low power circuit design based on heterojunction tunneling transistors (HETTs)

Low power circuit design based on heterojunction tunneling transistors (HETTs)

Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting

Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

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