A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load

Abstract

This paper proposes a self-biased sub-threshold CMOS voltage reference for ultra-low-power application. In the current generation path, a source degeneration active load (SDAL) is added to reduce the variation of the reference current (IR) which helps to produce a stable voltage reference (VREF). Moreover, by utilizing the line sensitivity (LS) improving circuit, the dependence of VREF on the supply voltage (VDD) can be largely reduced. The proposed design is fabricated in a standard 0.18-µm CMOS process. 11-chip measurement results show the prototype design can provide an 147.1 mV average voltage with a minimum power consumption of 353 pW at 27 ℃. The line sensitivity (LS) is only 0.014%/V, while the power supply rejection ratio (PSRR) at 10 Hz is -68 dB. The average temperature coefficient (TC) is 72 ppm/°C from -20 °C to +80 °C, and the die area is only 0.0019 mm 2 .