A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine

A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications

“…Furthermore, a full-utilization mode is designed by further increasing the parallelism of views and reusing the decoder bus to increase the output bandwidth. The throughput of 216fps corresponding to 9 views @ 24fps is achieved for QFHD, and is 12.5-to-40.5× higher than the previous works [4][5].…”

“…First, a hardware-oriented 6D FVVS flow is introduced along with the corresponding architecture to solve the first two design challenges. A maximum 1911MPixel/s throughput is achieved, and is 9-to-40.5× higher than the previous works [4][5][6]. Second, the cachebased texture reorder architecture with the dynamic warping reference frame selection (DWRFS) scheme reduces the external memory bandwidth by 95.7% in view synthesis.…”

“…In this case, two adjacent pixels in the reference view may be warped to the arbitrary positions in the virtual view according to their depth and epipolar geometry. Horizontal raster-scan-based scheduling [4][5] cannot deal with these irregular pixel relationships and can only support 1D horizontal shifts in the view synthesis. (3) The block-based memory accessing of reference pixels is not suitable for FVVS because of the processing nature of the irregular pixel access.…”

“…31.5GB/s system memory bandwidth is thus required for each virtual view in QFHD. State-of-the-art 3DTV chips cannot solve the issues above [4][5][6].…”