A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture

Kirihata, T.; Mueller, Georg; Ji, Bing; Frankowsky, G.; Ross, Joe; Terletzki, H.; Netis, D.; Weinfurtner, O.; Hanson, David R.; Daniel, George; Hsu, L.; Sotraska, D.W.; Reith, A.M.; Hug, M.A.; Guay, K.P.; Selz, M.; Poechmueller, P.; Hoenigschmid, H.; Wordeman, M.R.

doi:10.1109/4.799866

Cited by 15 publications

(2 citation statements)

References 24 publications

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“…The folded-bitline memory cell has been the sole type of cell for the last 20 years because of its noise-canceling capability [3]. With the help of a self-aligned contact process, this type of cell has reached its minimum size of ( : feature size) [4]. The greater difficulty of device miniaturization and the increasing cost of fabrication in the 0.1-m era lead, however, to a requirement for new memory cells which are smaller than .…”

Section: Introductionmentioning

confidence: 99%

A low-impedance open-bitline array for multigigabit DRAM

Sekiguchi

Itoh

Takahashi³

et al. 2002

IEEE J. Solid-State Circuits

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The noise-generating mechanisms inherent in the open-bitline DRAM array using the 6 2 (: feature size) memory cells and techniques for reducing the noise are described. The sources of differential noise coupled to the paired bitlines laid out in two arrays are the p-well, cell plate, and the group of nonselected wordlines. It was found, by simulation and by experiment with a 0.13m 256-Mb test chip, that the level of noise is dramatically reduced by using a low-impedance array with careful layout featuring low-resistivity materials, tight bridging between pairs of adjacent arrays, and a small array, achieving a comparable level of noise to that seen in the twisted and folded-bitline array. On basis of these results, it turns out that the open-bitline array has a strong chance of revival in the multigigabit generation, as long as these noise reduction techniques are applied.

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Section: Introductionmentioning

confidence: 99%

A low-impedance open-bitline array for multigigabit DRAM

Sekiguchi

Itoh

Takahashi³

et al. 2002

IEEE J. Solid-State Circuits

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“…T ECHNOLOGY advancement such as faster processors, multimedia extension algorithms, serial buses, and accelerated graphics ports is driving the need for a memory system with higher bandwidth and larger density. Doubledata-rate (DDR) synchronous DRAM (SDRAM) [1], [2] is an appropriate memory solution for systems ranging from multimedia-intensive PC's, high-end workstations, and servers to embedded communications systems such as graphics, cache, and main memory. DDR SDRAM, being an evolutionary architecture from SDRAM, features the doubled data rate at both the rising and falling edges of the clock and the use of the bidirectional data strobe for accurate data fetching to and from the memory controller.…”

Section: Introductionmentioning

confidence: 99%

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Yoon

Cha

Yoo³

et al. 1999

IEEE J. Solid-State Circuits

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A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-m process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated.

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A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture

Cited by 15 publications

References 24 publications

A low-impedance open-bitline array for multigigabit DRAM

A low-impedance open-bitline array for multigigabit DRAM

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

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