A 3D Convolution Accelerator Implemented on FPGA Using SDSoC

Ordonez, Jhon; Sahonero-Alvarez, Guillermo

doi:10.1109/iestec46403.2019.00126

Cited by 2 publications

(2 citation statements)

References 6 publications

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“…. Summarizing table of the scientific works discussed in section 4, related to image and signal processing, visual recognition, and hardware resource management using the ZCU102 platform Work Application Benefits Liu et al [55] Hardware Multi-View decoder High parallel High throughput (11x faster compared to the software implementation) Huang et al [56] Digital Pre-Distorsion system Hardware-efficient High-bandwidth scalability Ordoñez et al [57] 3D…”

Section: Discussionmentioning

confidence: 99%

“…A 3D convolutional neural networks (CNNs) accelerator, suitable for embedded systems, is described in [57]. The accelerator employs a pipelined architecture and implements parallel computations using several multiply-and-accumulate (MAC) units to accelerate the inference task in CNNs; each vector performs simultaneously three vector convolutions.…”

Section: High-throughput Data Processing Applications Using Xilinx Zynq Ultrascale+ Mpsoc Zcu102mentioning

confidence: 99%

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FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

et al. 2021

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The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the wellknown AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management.

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Section: Discussionmentioning

confidence: 99%

Section: High-throughput Data Processing Applications Using Xilinx Zynq Ultrascale+ Mpsoc Zcu102mentioning

confidence: 99%