A 3D IC BIST for pre-bond test of TSVs using ring oscillators

Abstract

Abstract-3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues, especially for TSVs. In this paper we propose a novel Built-In-Self-Test (BIST) architecture for pre-bond testing of TSVs in 3D stacked integrated circuits. The main idea is to measure the variation of TSVs capacitances in order to detect defective TSVs. The BIST architecture is based on ring oscillators, frequencies of which depend on TSVs capacitances. The proposed BIST is integrated within the JTAG standard. This paper presents spice simulation results and logic synthesis results of the proposed TSV ring oscillator structure using a 65 nm CMOS technology, including 10 µm diameter TSV middle technology. Due to local process variations, the proposed test architecture is limited in accuracy; it detects only large capacitive faults on TSVs.

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

“…This would essentially constitute an automated approach to circumvention of localised board issues. Beyond this however, there is a great need for further work in interconnect-level fault detection they represent critical points of failure and methods are confined to production test [95].…”

A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs

“…A cost-benefit analysis was carried out for sharing MBIST for multiple memory dies and integrating MBIST controllers on logic dies. BIST solutions based on ring oscillators for pre-bond testing of TSVs were proposed in [18], [19]. For post-bond testing of TSVs, a March test was developed for detecting crosstalk faults in neighboring TSVs [20].…”

Extreme ultraviolet lithography and three dimensional integrated circuit—A review

“…In order to effectively control the manufacturing costs, different levels of tests in fabrication processes should be conducted by using pre-bond test, mid-bond test, and post-bond test. 67,68 Pre-bond test targets classic logic of individual dies on the wafer level and unbounded TSVs; mid-bond targets partially assembled stacks; and post-bond test targets final circuit tests.…”

“…In the last few years, several pre-bond test strategies were proposed such as built-in self test (BIST) structure, 67,69,70 scan switch network (SSN) structure, 71 and vertically addressed test structures (VATS). 72 Design rules play a key role in the physical design of 3D ICs.…”