A 3x blind ADC-based CDR

Abstract

This paper uses a 3-bit ADC to blindly sample the received data at 3x the baud rate to recover the data. By moving from 2x to 3x sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu's 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16 FR4 channel.

4×, 3‐level, blind ADC‐based receiver

“…for the 48‐inch channel), 15 mW of which is consumed by the clock divider. Compared with [8], that in this Letter consumes similar power in the clock while consuming half the digital power. Owing to the reduced number of comparator uses per UI, the ADC power is also expected to drop by about 50%, but the measured ADC power shows only a drop of 20%.…”

“…The area of each block is shown in this Figure. The total area is ∼50% smaller than the total area of the 3× design in [8]. The total measured power of the chip is 63.5 mW (12.7 mW/Gbit/s) without the CTLE (i.e.…”

“…The DD block selects the sample closest to the UI centre as the transmitted bit. This is unlike the DD block in [8] in which a second‐order interpolation was needed to accurately estimate the UI centre for use in the digital DFE. The DD block selects one sample in each UI window that is closest to the picking phase, defined as Φ PICK = Φ AVE + 0.5 UI, for both the POS and NEG sets.…”

“…Previous blind ADC‐based CDRs [4–8] consumed a major portion of their power in their ADCs to sample the received data at high resolutions (5 bits in [4] and 3 bits in [8]). These high resolutions were needed for the digital blocks following the ADCs to accurately recover the value and the phase of the data.…”

“…To reduce power consumption, the ADC resolution ( n ) must be reduced. The corresponding loss in voltage (amplitude) resolution can be partially compensated by increasing the time resolution by means of the oversampling ratio (OSR) [8]. Assuming a flash ADC architecture is used, the analogue power consumption of the ADC is proportional to the number of comparators used for each unit interval (UI): (2 n − 1) × OSR.…”