A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding

Kubendran, Rajkumar; Park, Jongkil; Sharma, Ritvik; Kim, Chul; Joshi, Siddharth; Cauwenberghs, Gert; Ha, Sohmyung

doi:10.1109/iscas45731.2020.9180458

Cited by 3 publications

(4 citation statements)

References 8 publications

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“…Several area-and energy-efficient LC-ADCs have been presented in [23], [10], and [24]. An adaptive sampling scheme has been presented in [23] and achieves low power consumption (61 nW in [23]).…”

Section: A Lc-adc With the Offset Calibrationmentioning

confidence: 99%

“…Weltin-Wu and Tsividis [10] implemented an offset calibration and improved its SNDR, and at the same time increased the chip area. In [24], a two-tier approach has been proposed to achieve high SNDR (up to 57 dB) by applying more than ten comparators to track the analog signal with fine steps, at the expense of high power and large chip area. To mitigate the comparator offset without significantly increasing area, a new background comparator offset calibration is explored in this work.…”

Section: A Lc-adc With the Offset Calibrationmentioning

confidence: 99%

See 1 more Smart Citation

An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves

Corradi

Shi

et al. 2022

IEEE J. Solid-State Circuits

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Section: A Lc-adc With the Offset Calibrationmentioning

confidence: 99%

Section: A Lc-adc With the Offset Calibrationmentioning

confidence: 99%

An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves

Corradi

Shi

et al. 2022

IEEE J. Solid-State Circuits

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“…Ref. [16] presented a two-stage "5 + 5" C-ADC architecture that is more energy efficient than the LC-ADC while maintaining the same precision. The power consumption at bandwidths of 1 Hz-200 kHz is 160-426 µW.…”

Section: Introductionmentioning

confidence: 99%

A 0.49–4.34 μW LC-SAR Hybrid ADC with a 10.85-Bit ENOB and 20 KS/s Bandwidth

Tang,

Xu,

et al. 2024

Electronics

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This paper presents a level-crossing successive-approximation-register (LC-SAR) hybrid analog-to-digital converter (ADC) that combines an LC ADC with an SAR ADC, which may be used for Internet of Things (IoT) random sparse event scenarios. The sampling frequency of a traditional LC ADC is usually proportional to the maximum instantaneous rate of change of the input signal; therefore, a higher input signal frequency inevitably leads to higher system power consumption. However, the proposed hybrid ADC uses the input level difference between the two moments before and after level-crossing detection, thereby ensuring a higher conversion precision and lower power consumption, even at higher input signal frequencies. Compared with traditional LC ADC or SAR ADC, the proposed hybrid ADC combines the ultralow-power advantage of LC ADC with the high-precision advantage of SAR ADC in converting IoT data with sparse characteristics such as ECG, EEG, and brain potential. The LC-SAR hybrid ADC is designed with a 0.18 μm CMOS process and consumes 4.34 μW at a 1.8 V supply voltage, achieving an SNDR of 67.41 dB and a bandwidth of 20 kHz. The spectrum analysis result was 10.85 ENOB when the input sinusoidal signal was 14.975 kHz. When inputted with an ECG signal, the system power consumption was as low as 0.49 μW. Furthermore, the proposed hybrid ADC obtained a good figure of merit, with FoMw and FoMs reaching 58.8 fJ/conv.steps and 164 dB, respectively. Compared to a conventional uniform sampling ADC, approximately 80% of the power savings and an 8x compression ratio can be achieved in physiological signal acquisition applications.

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“…Thus, the event-driven ADC has attracted much attention in sparse signal processing. It is more efficient than traditional ADC with a fixed sampling rate because the invalid data during the inactive period of the sparse signal can be discarded [4][5].…”

Section: Introductionmentioning

confidence: 99%

A Fixed-Window Level-crossing ADC with a Single Comparator

Wei

Tong

Xin

2022

J. Phys.: Conf. Ser.

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A fixed-window level-crossing analog-to-digital converter (LC-ADC) with a single comparator is proposed for the biomedical field. In this paper, a signal varying direction detection circuit is proposed to judge the trend of the input signal, instead of the low-precision comparator in the modified LC-ADC. The proposed LC-ADC utilizes only one continuous-time comparator instead of multiple comparators in traditional LC-ADC, leading to simplified implementation and significantly reducing the power consumption. The post-layout simulation results show that the power consumption of the proposed new signal varying direction detection circuit is significantly reduced, accounting for only 25.6% of the high-precision continuous-time comparator. Designed with a 0.18 μm CMOS technology, the core area of this LC-ADC is 0.007 mm2. With a 1.8 V supply and 1 kHz input signal frequency, it achieves 73.1-dB SNDR by consuming 20.1 μW power. The figure-of-merit value is 19.3 mm2·fJ/Conversion.

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A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding

Cited by 3 publications

References 8 publications

An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves

An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves

A 0.49–4.34 μW LC-SAR Hybrid ADC with a 10.85-Bit ENOB and 20 KS/s Bandwidth

A Fixed-Window Level-crossing ADC with a Single Comparator

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