A 4.32&amp;#x007E;8.64-GHz receiver front-end with variable gain amplifier and I/Q mixer for 60-GHz heterodyne system in 65nm CMOS technology

This paper presents a 60 GHz CMOS I/Q receiver for the high-speed wireless communication system. It consists of a low noise amplifier, single-to-differential (S2D) amplifier, passive mixer, buffer amplifier with passive I/Q generator, and wideband baseband amplifier (BBA) stage. The measured conversion gain of 51 dB is achieved. The baseband bandwidth of 300 MHz is achieved from 57 GHz to 60 GHz. The 90° tandem coupler was implemented for I/Q signal generation, which has a phase error of <7° and an amplitude imbalance of <2 dB from 55 to 62 GHz. The Marchand balun is used to convert the I/Q signal to the differential, which has a phase error of <4°. A 60 GHz CMOS I/Q receiver is designed and fabricated, using a commercial 40 nm CMOS bulk process. The size of the receiver is 2.02 × 1.45 mm2, including the pads. The circuit is operated from a 0.9 V supply. The power consumption is 172 mW at maximum gain mode.

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A 60 GHz CMOS I/Q Receiver for High-Speed Wireless Communication System

Bhatta

Baek

Kim

2022

Applied Sciences

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A 4.32~8.64-GHz receiver front-end with variable gain amplifier and I/Q mixer for 60-GHz heterodyne system in 65nm CMOS technology

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A 60 GHz CMOS I/Q Receiver for High-Speed Wireless Communication System

A 60 GHz CMOS I/Q Receiver for High-Speed Wireless Communication System

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