A 4.5 mW 3–5 GHz low‐noise amplifier in 0.25‐μm silicon‐on‐insulator CMOS process for power‐constraint application

Abstract

A 1.5 V 4.5 mW 3–5 GHz low‐noise amplifier (LNA) suitable for power‐constraint application is implemented in a 0.25‐μm silicon‐on‐insulator CMOS process.The designed LNA with good input and output impedance matching exhibits gain of 10.3 dB and 2–2.9 dB noise figure within the 3–5 GHz band. Moreover, the −3 dB bandwidth of the presented LNA is insensitive to process corner variations. A third‐order input intercept point of −5 dBm is also achieved for the LNA at 3.6 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:89–93, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27262

A miniaturized 2.4-GHz CMOS low-noise amplifier using a gate-source coupling technique

“…Figure 1 shows a simplified schematic of a typical LNA. Generally, the source degeneration technique using an inductor, L SD , is popular to improve the NF [3][4][5][6][7]. Additionally, a shunt inductor, L IN , is used to cancel out the parasitic capacitance induced by the gate of the MN, as shown in Figure 1.…”