A 4.5Tb/s 3.4Tb/s/W 64&amp;#x00D7;64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS

Satpathy, Sudhir; Sewell, Korey; Manville, Thomas; Chen, Yen‐Po; Dreslinski, Ronald G.; Sylvester, Dennis; Mudge, Trevor; Blaauw, David

doi:10.1109/isscc.2012.6177098

Cited by 18 publications

(18 citation statements)

References 2 publications

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“…In particular, to support a speedup of two in a router providing 10Gb/s/port each tile will implement a memory throughput of 60Gb/s using six parallel SRAM banks, each 32 bits wide, 4K words high, and running at 310MHz. Total switch memory will be 96 Mbits on 230mm 2 , where additional tiles can be accommodated on a ring around the tile matrix [8] [9]. Comparing this 96-Mbit memory enabled by CIOQ to the 696-Kbit memory reported for HQ by Scott et al [4], CIOQ offers a fair improvement.…”

Section: Overall Cost and Performancementioning

confidence: 94%

“…The new direction for research in Networks-on-Chip (NoC's) is opened towards replacing the multi-hop mesh overheads [14][15] with high-radix crossbar switches [8][9][10] [11]. Recently, Sewell et al [9] and Abeyratne et al [10] showed that NoC's employing high-radix crossbar switches achieve improvement up to 2× in application execution time and 2× in NoC energy by reducing the diameter and increasing the throughput of the NoC.…”

Section: Comparison With the Swizzle Switchesmentioning

confidence: 99%

“…Recently, Sewell et al [9] and Abeyratne et al [10] showed that NoC's employing high-radix crossbar switches achieve improvement up to 2× in application execution time and 2× in NoC energy by reducing the diameter and increasing the throughput of the NoC. Earlier, the same group had demonstrated a custom, SRAM-style prototype of another "tiny-tera" onchip crossbar switch, called Swizzle Switch [8].…”

Section: Comparison With the Swizzle Switchesmentioning

confidence: 99%

“…We relocate our switch to newer, 45nm layouts in Section 5, where we as well cover the spare space for larger crossbars. Finally, we compare our design with the recently-proposed Swizzle Switches [8][9] [10] in Section 6, and conclude our article. Fig.…”

Section: Introductionmentioning

confidence: 99%

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The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches

Passas¹,

Katevenis

Pnevmatikatos

2015

IEEE Micro

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High-radix single-chip routers have emerged as efficient building blocks for interconnection networks. It is too believed that at high radices hierarchical switch architectures are needed as crossbars scale with the square of router radix. This article proposes a novel micro-architecture that allows flat crossbar switches to scale to 128 ports supporting 32Gb/s/port while occupying 4.9mm 2 and consuming 4.2W, or supporting 64Gb/s/port at 7.5mm 2 and 7.5W, in 45nm CMOS. Key features include deep crossbar pipelining to cope with wire delay, a novel cross scheduler architecture to reduce wiring complexity, and catalytic custom gate placement within standard Electronic Design Automation (EDA) flows. Thus, it is also shown that, on chip, crossbar speedup and Combined Input-Output Queuing (CIOQ) is better than Hierarchical Queueing (HQ) providing top performance with orders of magnitude lower memory cost. Finally, a comparison with the recently-developed Swizzle-Switch prototypes is plotted and the potential of high-radix crossbars for System-on-a-Chip interconnects is advocated.Index Terms-On-chip interconnection networks, packet-switching networks, VLSI † Manolis Katevenis is also with the

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Section: Overall Cost and Performancementioning

confidence: 94%

Section: Comparison With the Swizzle Switchesmentioning

confidence: 99%

Section: Comparison With the Swizzle Switchesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches

Passas¹,

Katevenis

Pnevmatikatos

2015

IEEE Micro

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“…Authors in [17] used the bus to efficiently handle broadcast and multicast messages reducing network latency. In [18], authors introduce crossbars in NoC environment and used them to implement an efficient invalidation MOESI protocol.…”

Section: Related Workmentioning

confidence: 99%

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the networkon-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-onchip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol -and hence its resources -, and moving this complexity to the network, leads to a global decrease in power consumption meanwhile area is barely affected. Benefits of our proposal are due to the high-throughput and low delay of the network, but also due to the simplicity of the coherence protocol. The proposed network and protocol minimizes communication amongst cores when compared to traditional solutions based either on 2D-mesh topologies or in directory-based protocols.

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Circuit design of Clos-based on-chip interconnection networks

Jiang

Yang

2016

Microprocessors and Microsystems

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Single-hop non-blocking networks have the advantage of providing uniform latency and throughput, which is important for cache-coherent network-on-chip systems. This paper focuses on high performance circuit designs of multi-stage non-blocking networks as alternatives to crossbars. Existing work shows that Benes networks have much lower transistor count and smaller circuit area but longer delay than crossbars. To reduce the timing delay, we propose to design the Clos network built with larger size switches. Using less than half number of stages than the Benes network, the Clos network with 4x4 switches can significantly reduce the timing delay. The circuit designs of both Benes and Clos networks in different sizes are conducted considering two types of implementation of the configurable switch: with NMOS transistors only and full transmission gates (TGs). The layout and simulation results under 45nm technology show that the TG-based implementation demonstrates much better signal integrity than its counterpart. Clos networks achieve average 60% lower timing delay than Benes networks with even smaller area and power consumption.

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A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS

Cited by 18 publications

References 2 publications

The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches

The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Circuit design of Clos-based on-chip interconnection networks

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