A 4.6-<i>μ</i>m, 127-dB Dynamic Range, Ultra-Low Power Stacked Digital Pixel Sensor With Overlapped Triple Quantization

Ikeno, Rimon; Mori, K.; Uno, Masayuki; Miyauchi, Katsuki; Isozaki, Toshiyuki; Takayanagi, Isao; Nakamura, Junichi; Wuu, Shou-Gwo; Bainbridge, Lyle; Berkovich, Andrew; Chen, Song; Chilukuri, Ramakrishna; Gao, Wei; Tsai, Tzung‐Jiun; Liu, Chiao

doi:10.1109/ted.2021.3121352

Cited by 13 publications

(17 citation statements)

References 28 publications

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“…The linear photoresponse in high-gain ADC operation (4×) is demonstrated as well. For FPN, we have confirmed two major contributing factors, one is a dc offset variation in the first-stage amplifier in the comparator due to its limited dc gain and the other is the delay variation in the comparator mainly due to the bias current variation [18]. The pixel-topixel photoresponse non-uniformity (PRNU) was 1.5% around 50% of PD saturation.…”

Section: Ts Modementioning

confidence: 68%

“…Therefore, the TS mode in the 3Q scheme is referred to as the TTS mode [17]. Note that the TTS mode in the 3Q scheme operates in a low conversion gain mode with the sense node capacitance being the sum of the FD capacitance and the additional capacitance C S inside the pixel to obtain a smooth transition in the photo-transfer characteristic from the TTS mode and the following linear ADC mode with low conversion gain, named FDADC mode [18]. On the other hand, the minor signal gap in the 2Q scheme cannot be intrinsically avoidable because an individual junction point in a photoresponse of two quantization scheme could not be fit into the desirable ADC operation range mainly due to PD full well variation (Q PD ), and that component is discussed Section IV.…”

Section: Q Mode Schemementioning

confidence: 99%

“…In such context, we have developed a stacked DPS with a triple quantization (3Q) scheme that achieves 127-dB DR and ultralow power of 5.7 mW at 30 frames/s with 10 bits/pixel ADC in a 4.6-μm pixel size [17], [18].…”

mentioning

confidence: 99%

“…The scheme we have adopted to realize the 127-dB DR with only 9-bit resolution was a combination of compressive coding using the time-to-saturation (TTS) quantization scheme and two linear ADCs [19]. Although using fewer bits may result in fine image details not being captured [7] and the combined three different operation modes may result in poorer SNR characteristics, especially at the junction points between two different operation modes, the obtained reconstructed linear photoresponse in the 3Q scheme exhibits the SNR gaps between modes approximately 4 dB [18]. Thus, the compressed representations in this scheme are best suited for CV applications, where the relevant information relies on image features [17]- [19].…”

mentioning

confidence: 99%

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A 4.0 μm Stacked Digital Pixel Sensor Operating in a Dual Quantization Mode for High Dynamic Range

Mori¹,

Yasuda²,

Miyauchi³

et al. 2022

IEEE Trans. Electron Devices

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It is anticipated that ubiquitous computer vision (CV) and artificial intelligence (AI) applications used on mobile devices will grow significantly. Such applications require battery-powered, always-on mobile devices to support indoor/outdoor, day/night usages. A global shutter (GS), stacked digital pixel sensor (DPS) is a promising candidate to meet such requirements because of its potential for ultralow-power, ultrahigh dynamic range (HDR), and a small form factor. This article presents a prototype 4.0-µm stacked DPS operating in its dual quantization (2Q) to realize HDR. The 4.0-µm DPS pixel is formed with two layers, a backside illuminated pinned photodiode (PD) pixel on the top layer and an in-pixel analog-to-digital conversion (ADC) circuit with 9-bit static random access memory (SRAM) on the bottom layer. A Cu-to-Cu hybrid bonding (HB) technology is used to connect the two layers via pixel-level interconnect. In the 2Q scheme, a time-stamp (TS) quantization and a linear ADC are performed sequentially in the same frame, which extends the dynamic range (DR) with a small number of ADC bits of 9. The DPS with a 1024 × 832 pixel array has achieved a single-exposure ultra HDR of 107 dB in a single frame. The nonlinear conversion characteristic of the TS mode provides an equivalent full well capacity (FWC) of 2000ke − , while the noise floor in the linear ADC mode is 8.3e − . Index Terms-CMOS image sensor (CIS), computer vision (CV) sensor, digital pixel sensor (DPS), global shutter (GS), high dynamic range (HDR), noise analysis, stacked process. I. INTRODUCTIONT HE digital pixel sensor (DPS) architecture [1], [2] was studied with high expectation to achieve high-speed, lowpower, and high dynamic range (HDR) [3], [4] in a global shutter (GS) operation in 1990s to early 2000s. However, its Manuscript

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Section: Ts Modementioning

confidence: 68%

Section: Q Mode Schemementioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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A 4.0 μm Stacked Digital Pixel Sensor Operating in a Dual Quantization Mode for High Dynamic Range

Mori¹,

Yasuda²,

Miyauchi³

et al. 2022

IEEE Trans. Electron Devices

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“…A similar method is to control exposure for a block of pixels, as shown in [20] [21]. In [22] a 512×512 array with 4.6 µm pitch on a 3D-IC achieves 127 dB DR by combining dual conversion gain with timeto-saturation detection. Key advantages are the high spatial fidelity achieved with a pixel-parallel readout, however there is non-continuity in the SNR response due to the three photosensing regimes.…”

Section: Introductionmentioning

confidence: 99%

A Method to Achieve High Dynamic Range in a CMOS Image Sensor Using Interleaved Row Readout

et al. 2022

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We present a readout scheme for CMOS image sensors that can be used to achieve arbitrarily high dynamic range (HDR) in principle. The linear full well capacity (LFWC) in high signal regions was extended 50 times from 20 ke − to 984 ke − via an interlaced row-wise readout order, whilst the noise floor remained unchanged in low signal regions, resulting in a 34 dB increase in DR. The peak signal-to-noise ratio (PSNR) is increased in a continuous fashion from 43 dB to 60 dB. This was achieved by summing user-selected rows which were read out multiple times. Centroiding uncertainties were lowered when template-fitting a projected pattern, compared to the standard readout scheme. Example applications are aimed at scientific imaging due to the linearity and PSNR increase.

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BlissCam: Boosting Eye Tracking Efficiency with Learned In-Sensor Sparse Sampling

Feng,

Ma,

Zhu

et al. 2024

2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)

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A 4.6-μm, 127-dB Dynamic Range, Ultra-Low Power Stacked Digital Pixel Sensor With Overlapped Triple Quantization

Cited by 13 publications

References 28 publications

A 4.0 μm Stacked Digital Pixel Sensor Operating in a Dual Quantization Mode for High Dynamic Range

A 4.0 μm Stacked Digital Pixel Sensor Operating in a Dual Quantization Mode for High Dynamic Range

A Method to Achieve High Dynamic Range in a CMOS Image Sensor Using Interleaved Row Readout

BlissCam: Boosting Eye Tracking Efficiency with Learned In-Sensor Sparse Sampling

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