A 4.6-ppm/°C High-Order Curvature Compensated Bandgap Reference for BMIC

Zhu, Guangqian; Yang, Yintang; Zhang, Qidong

doi:10.1109/tcsii.2018.2889808

Cited by 33 publications

(33 citation statements)

References 14 publications

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“…Typically bandgap reference is designed with PNP bipolar transistors, which results in the amplification of amplifier offset and flicker noise. Recently, the use of NPN bipolar in Bandgap reference [3]- [7] has gained traction due availability of triple well CMOS process. The inherent gain of the NPN transistors eases the specification of the amplifier.…”

Section: Introductionmentioning

confidence: 99%

“…Vbe of the transistor is having 2nd order terms (i.e., curvature), which will results in significant temp-co. Several techniques have been proposed to tackle this problem, the Curvature compensation is proposed by [4] lowers the virtual node impedance of opamp, resulting in higher flicker noise and offset amplification. This work exploit's the base resistance of the BJT for the curvature compensation [3]. The mechanism of the curvature compensation is explained analytically and is shown that single point trim brings the worst-case accuracy to 12 ppm/ • C with typical being 4ppm/ • C. The paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

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A 15uW, 12 ppm/^°C Curvature Compensated Bandgap in 0.85V Supply

Nagulapalli

Palani²,

Agarwal³

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, a curvature-compensated bandgap reference circuit is presented which generates 0.538V from 0.85V supply voltage. The PTAT voltage generated in the bandgap core is added to the partial CTAT voltage to generate the sub-bandgap reference, reducing the CTAT current mirror mismatch. Furthermore, this architecture eases the opamp's requirements on offset and flicker noise significantly and doesn't require sophisticated techniques, such as chopping. A novel curvature compensation scheme is proposed and validated across PVT simulations and achieves 12 ppm/ • C with a single point trim. The proposed bandgap consumes a power of 15 µW and occupies an area of 7315 µm 2 in TSMC 28nm.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 15uW, 12 ppm/^°C Curvature Compensated Bandgap in 0.85V Supply

Nagulapalli

Palani²,

Agarwal³

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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show abstract

“…The biasing circuit and variation in the power supply also contribute to the noise. Hence, a clock generator requires a low-noise voltage regulator with a high PSRR to suppress supply and unwanted bias circuitry noise [20][21][22][23][24][25].…”

Section: Introductionmentioning

confidence: 99%

A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator

Agarwal

Oh‐e

2021

Electronics

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A chopper-embedded bandgap reference (BGR) scheme is presented using 0.18 μm CMOS technology for low-frequency noise suppression in the clock generator application. As biasing circuitry produce significant flicker noise, along with thermal noise from passive components, the proposed low-noise chopper-stabilized BGR circuit was designed and implemented for wide temperature range of −40 to 125 °C, including a startup and self-biasing circuit to reduce critical low-frequency noise from the bias circuitry and op amp input offset voltage. The BGR circuit generated a reference voltage of 1.25 V for a supply voltage range of 2.5–3.3 V. The gain of the implemented BGR operational transconductance amplifier is 84.1 dB. A non-overlapping clock circuit was implemented to reduce the clock skew effect, which is also one of the noise contributors. The noise analysis of a chopped bandgap voltage reference was evaluated through cadence periodic steady-state (PSS) analysis and periodic noise (PNoise) analysis. The low-frequency flicker noise was reduced from 1.5 to 0.4 μV/sqrt(Hz) at 1 KHz, with the proposed chopping scheme in the bandgap. Comparisons of the noise performance of the chopper-embedded BGR, with and without a low-pass filter, were also performed, and the results show a further reduction in the overall noise. A reduction in the flicker noise, from 181.3 to 10.26 mV/sqrt(Hz) at 100 KHz, was observed with the filter. All circuit blocks of the proposed BGR scheme were designed and simulated using the EDA tool HSPICE, and layout generation was carried out by Laker. The BGR architecture layout dimensions are 285.25 μm × 125.38 μm.

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“…However, this will induce switching noise in the system. In [11], the BGR can work with high supply voltage from 3.5 V to 5 V. However, the power consumption is larger than 100 μW. In most reference circuits, a resistor is a common choice to generate PTAT current and PTAT voltage [6]- [10].…”

Section: Introductionmentioning

confidence: 99%