A 4.6GHz resonant global clock distribution network

Chan, S.C.; Restle, P.J.; Shepard, Kenneth L.; James, N.; Franch, R.

doi:10.1109/isscc.2004.1332734

Cited by 55 publications

(35 citation statements)

References 5 publications

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“…This issue is addressed by biasing the circuit with a decoupling capacitor (C d ) at the grounded end of the inductor as shown in Figure 1(a) [5]. This capacitance must be sufficiently large to cleanly separate the series and parallel resonant frequencies by satisfying…”

Section: A Resonant Theorymentioning

confidence: 99%

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Multi-frequency resonant clocks

LaCara

Lin

Guthaus

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Clock distribution networks consume a significant portion of total chip power in high-performance designs. Resonant clocks are one proposed method to lower this power in modern designs as well as a fewer required clock buffers. Recent resonant solutions are limited to optimal performance at one particular frequency which is problematic since dynamic frequency scaling is often used to lower overall system power. This paper introduces the first scheme to produce a clock distribution network with a tunable resonant frequency. Experimental results show the resonant frequency ranges from 1.2GHz to 2.6GHz while saving up to 41% of the power on the clock distribution network when compared to the non-resonant distribution.

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Section: A Resonant Theorymentioning

confidence: 99%

“…Previous resonant clock approaches include standing wave oscillators [2], rotary/salphasic clocks [3], [4] and resonant inductor-capacitor (LC) tanks [5]- [10]. Standing wave resonant clocks result in a constant phase but their amplitude varies depending on placement in the CDN.…”

Section: Introductionmentioning

confidence: 99%

Multi-frequency resonant clocks

LaCara

Lin

Guthaus

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Resonant clock distribution has the potential to reduce clock power and achieve low clock skew and jitter [3]. In this project, a two-phase resonant clock network with a programmable driver and loading has been designed and evaluated.…”

Section: Ghz-class Resonant Clockingmentioning

confidence: 99%

Design Technologies for Energy-Efficient VLSI Systems

Papaefthymiou¹

2007

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Public Reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. This project has investigated novel design technologies for energy-efficient VLSI systems. Its primary focus has been on charge-recovery circuits. These circuits achieve higher energy effieiency than their conventional counterparts by steering currents to flow across devices with low voltage drops, while recycling undissipated energy in parasitic capacitors. Previous investigations into charge recovery have resulted in complex circuits and architectures that are impractical for high-speed design. This project has led to the discovery of practical low-complexity charge-recovery circuits which achieve high energy efficiency and achieve clock frequencies in excess of 1GHz. The results of this research have been validated through silicon prototyping and experimentation. For four of the inventions resulting from this project, the University of Michigan has filed utility and provisional patent applications with the US Patent and Trademark Office.Marios C. Papaefthymiou 43715.20-CI 19 energy-efficient VLSI systems, charge-recovery circuits, low-complexity charge-recovery circuits

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“…Both traveling wave [1], [2], [3], [4] and standing wave [5] oscillators have been proposed in the literature. The typical configuration of these oscillators is a pair of closely spaced rings, implemented on higher metal layers on an IC.…”

Section: Introductionmentioning

confidence: 99%

A PLL design based on a standing wave resonant oscillator

Karkala

Bollapalli

Garg

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-In this paper, we present a new continuously variable high frequency standing wave oscillator, and demonstrate its use in generating the phase locked clock signal of a digital IC. The ring based standing wave resonant oscillator is implemented with a plurality of wires connected in a mobius configuration, with a cross coupled inverter pair connected across the wires. The oscillation frequency can be modulated by two means. Coarse modification is achieved by altering the number of wires in the ring that participate in the oscillation, by driving a digital word to a set of passgates which are connected to each wire in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the oscillations in the resonant ring. We have validated our PLL design in a 90nm process technology. 3D parasitic RLCs for our oscillator simulations were extracted, with skin effect accounted for. Our PLL has been implemented to provide a frequency locking range from ∼6 GHz to ∼9 GHz, with a center frequency of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56%.

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A 4.6GHz resonant global clock distribution network

Cited by 55 publications

References 5 publications

Multi-frequency resonant clocks

Multi-frequency resonant clocks

Design Technologies for Energy-Efficient VLSI Systems

A PLL design based on a standing wave resonant oscillator

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