A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET

Kim, Gain; Kull, Lukas; Luu, Danny; Braendli, Matthias; Menolfi, Christian; Francese, Pier Andrea; Yueksel, Hazar; Aprile, Cosimo; Morf, Thomas; Kossel, Marcel; Cevrero, Alessandro; Özkaya, İlter; Bae, Hyeon‐Min; Burg, Andreas; Toifl, Thomas; Leblebici, Yusuf

doi:10.1109/a-sscc47793.2019.9056940

Cited by 8 publications

(1 citation statement)

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“…While a TX pre-emphasis equalizer, a CTLE, and a DFE are necessary for error-free communication through a lossy electrical channel, the power consumption of those blocks is significant. For short-reach (SR) and long-reach (LR) channels, the energy efficiencies of 0.8-1.2pJ/b [16] and 3-5pJ/b [22], [23], respectively, are typically reported figures. Lowpower equalization/modulation/coding techniques have been explored to increase bandwidth-energy-efficiency.…”

Section: Wireline Interface Overviewmentioning

confidence: 99%

Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators

Lee

Kim

Park

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In convolutional neural network (CNN) accelerators, the dominant power consumption is caused by the access of external data memory. In addition, power and area occupied by I/O interfaces maintaining low bit-error-rate, e.g., 1e-15, grow as the data rate increases. Considering the inherent error resilience of the inference process in machine learning applications, the requirement of error-free communication in the data-path is controversial. In this paper, a custom CNN accelerator integrating a channel emulator is designed by using an FPGA to analyze the effect of the BER of an I/O transceiver on the image classification accuracy. In order to implement a channel emulator, a digital-domain look-up-table (LUT)-based 12-tap FIR filter is employed to create inter-symbol interference (ISI), and a PRBS31 generator is used as a noise source. The implementation was evaluated by running the ImageNet dataset on the FPGA-based custom accelerator (Virtex Ultrascale+) implementing VGG-16. The results show that the BER up to 1e-4 in the memory access has a negligible impact on the inference accuracy.

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Section: Wireline Interface Overviewmentioning

confidence: 99%