A 4-bit CMOS full adder of 1-bit hybrid 13T adder with a new SUM circuit

A 2x2 Bit Multiplier Using Hybrid 13T Full Adder with Vedic Mathematics Method

“…This is a significant achievement since a faster circuit can be obtained by using smaller technology without compromising the circuit functionality. The result shown that the proposed HFA is able to perform 70.28% faster than the original design in [8]. Both of these designs using the same algorithm and number of transistors counts, but these designs are different in the GPDK used and the power supply.…”

“…The 1-bit hybrid full adder (HFA) circuit was designed by constructing the full adder using three modules as shown in Figure 2 [8]. XOR circuit is inside Module I and with an inverter, a XOR-XNOR combination will be produced to drive the other two modules.…”

“…The design is based on a modified version of CMOS inverter and a PMOS pass transistor [9]. Module II is a new circuit being designed called unique sum circuit to produce output SUM for the HFA [8]. Only four transistors are used in this design as compared to the circuit designed by Suguna which used six transistors [10].…”