A 4-Channel 1.25–10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

Design Techniques for High-Speed I/Os: Challenges and Opportunities

“…It is also used solely for channels with negligible reflection and crosstalk [53,54]. Because the received symbol is severely attenuated, input offset voltage compensation is typically required in CTLE [55,56]. Unlike CTLE, nonlinear post-equalization removes post-cursors by subtracting estimated post-cursors directly from data symbols prior to slicing.…”

A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE

“…Therefore, the emulated n post-cursor ISI taps are noise free and in the summer block only ISI taps are canceled. This key point is the main advantage of DFE over analog equalizer [1,5,6].…”

“…This technique is the most effective approach for relaxing the timing constraint in feedback loops and is usually used in very high speed DFEs. The drawback of loop-unrolling technique is that by increasing the number of taps, area and power consumption grows exponentially, which is not suitable for low-power designs [6]. In CML logic based designs, soft decision technique in half-rate and quarter-rate architectures can be applied to relax the first feedback critical path [8].…”

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

“…Although continuoustime linear equalizer (CTLE) is a well-known and widely adapted technique for the compensation of ISI, it amplifies the unwanted high-frequency noise as well [2]. A decision feedback equalizer (DFE) can cancel the post-cursor ISI without any high-frequency noise enhancement [3].…”