A 4-level storage 4 Gb DRAM

Abstract

Bit-cost reduction is one of the most serious issues for file application DRAMs [l, 2, 31. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell reduction technology is needed.Multi-level storage is one circuit technology, that can reduce the effective cell size since it allows the storage of multiple voltage levels in a single memory cell functioning as a multi-bit memory [4,5,61. When four levels are stored in a single memory cell, the effective cell size is halved.A charge-coupling sense amplifier, charge-sharing restore, and time-shared sensing increase speed and reduce sense-circuit area for 4Gb DRAM.

Common Fallacies about Multivalued Circuits

“…M-valued SRAMs and DRAMs have been fabricated and tested by industrial companies in the 80's and the 90's, such as Hitachi [37], NEC [38] and [39], etc. They are detailed in [36].…”

Ternary circuits: why R=3 is not the Optimal Radix for Computation

“…Binary DRAMs use electrical charges to store bits in 1.5 T cells (1 transistor + 1 capacitance). M-valued SRAMs and DRAMs have been fabricated and tested by industrial companies in the 80's and the 90's, such as Hitachi [12], NEC [13] and [14], etc. They are detailed in [11].…”

Evolution of Technologies and Multivalued Circuits

“…M-valued SRAMs and DRAMs have been fabricated and tested by industrial companies in the 80's and the 90's, such as Hitachi [10], NEC [11] and [12], etc. They are detailed in [2].…”