A 4-READ 2-WRITE Multi-Port Register File Design Using Pulsed-Latches

Manivannan, T. S.; Srinivasan, Meena

doi:10.1109/iceca.2018.8474898

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…The power consumption saving is 58% compared to the literature by Wu et al [22], and literature by Suzuki et al [23] and Li et al [30] significantly reduces the power consumption, but the present design increases the operating frequency to 3.8 times of the original and has a larger data capacity. The literature by Manivannan and Srinivasan [28] uses a 28-nm process design, which is similar to the present design in terms of array size, number of ports, and operating speed, and the present design saves 81.91% in terms of power consumption.…”

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confidence: 78%

A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit

Zhao,

Zhang,

Wen

et al. 2023

IET Circuits, Devices & Systems

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Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm2 and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz.

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confidence: 78%