A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology

Ong, A.; Benyamin, S.; Cancio, J.; Condito, V.; Labrie, T.; Lee, Qinghung; Mattia, J.P.; Shaeffer, D.K.; Shahani, A.R.; Si, Xiaomin; Tao, Hai; Tarsia, M.; Wong, W.; Xu, Mingfei

doi:10.1109/jssc.2003.818565

Cited by 43 publications

(5 citation statements)

References 23 publications

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“…This enables the use of DQPSK for communication over longer distances on legacy fiber. The 3W power consumption is less than 25% of a first generation biCMOS SFI5 SERDES chipset [2], [3] and 45% less than a recent CMOS SFI5 SERDES chipset [9]. In addition, minimal use of inductors and adoption of the more recent SFI5.2 standard results in chip area more than 1/3 less than [9].…”

Section: Discussionmentioning

confidence: 99%

“…To replace legacy 10 Gb/s transponders in existing racks, strict power budgets must be met, especially for the SERDES ICs, which represent the largest component of power consumption. First generation 40 Gb/s SERDES were implemented in SiGe bipolar or biCMOS [2], [3], [6], [7]. The more recent 90 nm and below CMOS nodes afford a pure CMOS implementation, as has been demonstrated in several prototype designs [4], [8], [5].…”

Section: Introductionmentioning

confidence: 99%

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A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

Nedovic

Kristensson

Parikh

et al. 2009

2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium

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A 2 x 21.5-22.3 Gb/s to 4 x 10.7-11.2 Gb/s SFI5.2 compliant two-chip SerDes for a 40 Gb/s optical transponder module has been fabricated in 65 nm 12-metal CMOS. The deserializer receives 2 x 20 Gb/s data from a TIA and outputs SFI 5.2 4 x 10 Gb/s data and 10 Gb/s deskew channel. The serializer receives SFI5.2 inputs and outputs 2 x 20 Gb/s for the optical DQPSK modulator. Although inductor-peaked CML is needed in the deserializer 20 Gb/s input limiting amplifier (LA) and the serializer output stages, power reduction to 3 W for both IC's is effected by deserializing to 16 x 2.5 Gb/s internally and implementing the core logic using standard CMOS circuits.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

Nedovic

Kristensson

Parikh

et al. 2009

2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium

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“…The transceiver extends the circuit techniques previously described in [1, 2] that can offer the operating frequency of the 40-Gb/s transmitter and the 20-GHz PLL in a CMOS process with f T of less than 70 GHz, which is at most half as high as the competing SiGe, GaAs, or InP processes [3]. The techniques include single-transformer based shunt-and-double-series inductive peaking, negative feedback for bandwidth extension, and the use of pulsed latches for fast timing closure.…”

mentioning

confidence: 97%

“…For a wide capture range, good stability, small dither jitter, and high jitter tolerance, it is critical to minimize the feedback-loop latency in the bang-bang proportional control path. While the basic architecture for phase detection is similar to the one in [3], the final multiplexing stage is removed and the two sets of up/down signals separately drive the VCO via a set of small varactors for the fastest proportional control update. For the integral control, the up/down signals drive a charge pump and an integrating loop filter.…”

mentioning

confidence: 99%

A 40-Gb/s transceiver in 0.13-μm CMOS technology

Jeong-Kyoum

Kim

et al. 2008

2008 IEEE Symposium on VLSI Circuits

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A fully integrated 40-Gb/s transceiver is implemented in a 0.13-µm CMOS technology. This paper describes the challenges in designing a 20-GHz input sampler, a 20-GHz quadrature LC-VCO, a 20-GHz bang-bang phase detector, and a 40-Gb/s equalizer. The transceiver occupies 1.7 × 2.9mm 2 and dissipates 3.6W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2 15 -1 PRBS data is 1.85ps rms over a wire-bonded plastic ball grid array (PBGA) package, an 8-mm RO-4350B PCB trace, an on-board 2.4-mm connector, and a 1m-long 2.4-mm coaxial cable, while the recovered clock jitter is 1.77 ps rms . The measured BER is < 10 -14 .Introduction This paper presents a fully integrated 40-Gb/s transceiver implemented in the 0.13-µm CMOS technology, including a 32:1 serializer, a 1:32 deserializer, a 20-GHz clock generator PLL, and a binary clock and data recovery PLL. The transceiver extends the circuit techniques previously described in [1, 2] that can offer the operating frequency of the 40-Gb/s transmitter and the 20-GHz PLL in a CMOS process with f T of less than 70 GHz, which is at most half as high as the competing SiGe, GaAs, or InP processes [3]. The techniques include single-transformer based shunt-and-double-series inductive peaking, negative feedback for bandwidth extension, and the use of pulsed latches for fast timing closure. We extend these techniques to build a complete transceiver with new challenges being addressed in this paper: a half-rate input sampler for the 40-Gb/s data stream, a 20-GHz quadrature LC-VCO, a low-latency phase detector for the bang-bang controlled clock recovery PLL, and a simple 40-Gb/s equalizer for channel loss compensation.Receiver Architecture A block diagram of the implemented 40-Gb/s deserializing receiver is shown in Fig. 1. The receiver is composed of a linear equalizer, four half-rate samplers, a 2:32 multi-stage deserializer, a PRBS verifier, and a bang-bang clock recovery PLL. The four 20-GHz samplers latch the input voltage at the center and edge of the incoming 40-Gb/s NRZ data stream. The timing of the samplers is controlled by 20-GHz quadrature clocks. The phase detection logic following the samplers extracts the polarity of the phase error to adjust the VCO clock timing. The 2:32 deserializer consists of four cascaded 2:1 multiplexing stages that convert the 2-bit 20-Gb/s retimed data to 32-bit-wide, 1.25-Gb/s data. The clock frequencies required by the different stages are generated by a chain of divide-by-2 dividers. The frequency detector compares the last divided clock with a 625-MHz reference clock to assist the main phase-detection loop in acquiring the initial frequency lock.Building Blocks The proposed 20-GHz sampler shown in Fig. 2 uses a pulsed-latch based design to shorten the latency of a latch. The inductive peaking and conditional negative feedback

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“…Traditionally, INV, EF-INV, or EF-Cherry-Hooper topologies have been preferred for high-speed preamplifiers (e.g., [14]). All require on-chip 50-matching resistors, which add noise and reduce the sensitivity of the preamplifier.…”

Section: B High-sensitivity Transimpedance Preamplifiermentioning

confidence: 99%