A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13&amp;#x003BC;m CMOS Silicon-on-Insulator Technology

Narasimha, A.; Analui, B.; Balmater, E.; Clark, A.G.; Gal, Thomas J.; Guckenberger, D.; Gutierrez, S.; Harrison, Mark C.; Ingram, Ryan; Koumans, R.G.M.P.; Kucharski, D.; Leap, Kosal; Liang, Yi; Mekis, Attila; Mirsaidi, Sina; Peterson, Mark; Pham, T.H.; Pinguet, Thierry; Rines, David M.; Sadagopan, V.; Sleboda, T.J.; Song, Dalei; Wang, Yanxin; Welch, B.; Witzens, Jeremy; Abdalla, Sherif; Gloeckner, S.; Dobbelaere, P. De

doi:10.1109/ofc.2008.4528356

Cited by 35 publications

(26 citation statements)

References 2 publications

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“…The other approach is referred to as hybrid integration and involves the integration of a discrete device with a silicon photonic waveguide by means of intermediate micro-opto-electro-mechanical systems (MOEMS). Either end-coupling to an inverse taper or near-vertical coupling to a grating can be used 10,11 . Near-vertical coupling allows the laser die and associated optics to be placed off the chip, thus saving valuable chip real estate, and also allowing adding additional functional enhancements such as an optical isolator.…”

Section: Hybrid Integration Of Lasers On Silicon Photonic Platformmentioning

confidence: 99%

Packaging challenges for integrated silicon photonic circuits

Pavarelli¹,

Lee²,

O’Brien³

2014

Silicon Photonics and Photonic Integrated Circuits IV

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Cost-effective packaging of silicon photonic devices presents a significant bottleneck to commercialization of the technology. One way of addressing this packaging challenge is to use techniques that have been developed by the electronics industry and which also benefit from the use of advanced electronics assembly equipment. Even packaging processes such as fiber coupling can benefit from this approach, along with the hybrid integration of devices such as electronic components (e.g. modulator driver integrated circuits). In this paper, we will present developments made by our group towards achieving scalable fiber and electronic packaging processes that rely on electronic assembly techniques such as flip-chip assembly. We will also provide an overview of packaged prototypes being developed within our group for telecom and sensing applications and how these packaging technologies are now being made available to users through the ePIXfab foundry service.

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Section: Hybrid Integration Of Lasers On Silicon Photonic Platformmentioning

confidence: 99%

Packaging challenges for integrated silicon photonic circuits

Pavarelli¹,

Lee²,

O’Brien³

2014

Silicon Photonics and Photonic Integrated Circuits IV

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“…• The die contains all the high-speed analog circuits usually found in a transceiver (TIA, limiting amp, laser drivers, modulator driver, etc…) as well as large digital blocks to control the system and to communicate to the outside world through a digital bus [4].…”

Section: Transceiver Architecturementioning

confidence: 99%

Monolithically integrated high-speed CMOS photonic transceivers

Pinguet¹,

Analui²,

Balmater³

et al. 2008

2008 5th IEEE International Conference on Group IV Photonics

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“…In some cases integration can also change in more fundamental ways how opto-electronic building blocks interact with electronic circuitry, by removing the parasitic capacitance associated with flip-chip or wire bonding and by enabling easy, distributed access to optoelectronic components. For example, Luxtera has implemented a distributed Mach Zehnder interferometer (MZI) driver that drastically reduces power consumption [2]. This design is facilitated by the integration of the driver and the high speed phase modulator on the same chip, since a very large number of electrical contacts between these two building blocks are needed.…”

Section: Introductionmentioning

confidence: 99%

“…Several optical building blocks have been demonstrated already on Si: waveguides [3], high speed modulators [4], photodetectors [5], as well as complete transceivers. Luxtera recently introduced a 40 Gbps (4 channel, 10Gbps each) monolithic optical transceiver built on a Si CMOS platform [2]. While waveguiding and modulation can be done in Si and do not require the integration of new materials in the CMOS process, photodetection at long wavelengths (1.3 and 1.55 um) requires either Germanium or a III-V compound such as InGaAs.…”

Section: Introductionmentioning

confidence: 99%

10Gbit/s transceiver on silicon

Witzens¹,

Masini²,

Sahni³

et al. 2008

SPIE Proceedings

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We discuss our approach to monolithic integration of Germanium photodectors with CMOS electronics for high speed optical transceivers. Integration into the CMOS process and optimization of optical coupling into the devices is described, followed by a discussion on how the devices are deployed in 4×10 Gbs receiver and transmitter subsystems. We demonstrate -19 dBm optical sensitivity for a bit error rate of 1e-12. An improvement of several dB resulted from optimizing the transimpedance amplifier relative to a design that was targeted for hybrid integration with flip-chip photodetectors, in order to take advantage of the drastically reduced capacitance of the integrated photodetectors (below 20 fF). As an example of how the versatility of on-chip waveguides and integrated photodiodes can be used, we further describe how the Germanium photodetectors are deployed to obtain a fully autonomous Mach-Zehnder interferometer subsystem with built-in monitoring and control, that can be instantiated as a single cell in an IC design. A fully differential layout is implemented for optical, electro-optic and electrical components yielding very small mismatch between components and enabling control of the interferometer with a minimum penalty.

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A 40-Gb/s QSFP Optoelectronic Transceiver in a 0.13μm CMOS Silicon-on-Insulator Technology

Cited by 35 publications

References 2 publications

Packaging challenges for integrated silicon photonic circuits

Packaging challenges for integrated silicon photonic circuits

Monolithically integrated high-speed CMOS photonic transceivers

10Gbit/s transceiver on silicon

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