A 40 Gbps optical receiver analog front-end in 65 nm CMOS

Chou, Shun-Tien; Huang, Shih-Hao; Hong, Zheng-Hao; Chen, Wei-Zen

doi:10.1109/iscas.2012.6271598

Cited by 11 publications

(6 citation statements)

References 6 publications

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“…At 25 Gb/s, our W-APD provide a 1.7 dBm improvement over that of Yoshimatsu et al [7] while matching > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 that of Makita et al [8] at 40 Gb/s, as shown in figure 5. Reducing the TIA noise is an active area of research [16][17][18], with highly encouraging low noise of 14 pA/√Hz achieved at 40 Gb/s [16]. With the expected improvement in the TIA noise, it is imperative that the APDs should also be designed to exhibit low dark current and low excess noise to optimize the sensitivity.…”

Section: Resultsmentioning

confidence: 99%

InGaAs/InAlAs Avalanche Photodiode With Low Dark Current for High-Speed Operation

Xie

Zhang

Tan

2015

IEEE Photon. Technol. Lett.

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Waveguide InGaAs/InAlAs avalanche photodiodes (APDs) with high bandwidths (> 40 GHz) and low dark current (< 50 nA at 90% of breakdown voltage) were demonstrated. The excess noise is low, corresponding to k ~ 0.2 line in the local excess noise model. Using these values Bit Error Rate (BER) was calculated to assess the potential of our APDs. Calculated sensitivities of -21.5 dBm at 25 Gb/s and -14.2 dBm at 40 Gb/s are predicted for a BER of 10 -10 . Analysis showed that with lower amplifier noise, the low dark current and low excess noise from our APDs are necessary to optimize the sensitivity. IndexTerms-Avalanche photodiodes bandwidth, bit-error-rate, receiver sensitivity at 25 Gb/s

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Section: Resultsmentioning

confidence: 99%

InGaAs/InAlAs Avalanche Photodiode With Low Dark Current for High-Speed Operation

Xie

Zhang

Tan

2015

IEEE Photon. Technol. Lett.

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“…where ZT is the transimpedance gain, P, the power consumption and BW the system bandwidth. Compared with other designs from literature only [12] and [14] achieved a better FOM although our design has gain control and offset control for burst mode Data. The design from [16] has larger bandwidth but higher power consumption and no gain or offset control.…”

Section: IVmentioning

confidence: 69%

“…Alternative and more scalable transceiver configurations include 8x50Gb/s or 4x100Gb/s which call for wideband electrical transceivers with more stringent BW requirements >50GHz. However, most high-end TIAs, LAs and CDRs designed in CMOS technologies, operate with a BW of ~28GHz [12][13][14][15][16][17] and are not scalable for high data rates. We propose a receiver frontend operating at 64Gb/s with a bandwidth of 48GHz which would be compatible with a configuration of 6x64GB/s at 384Gb/s.…”

Section: Introductionmentioning

confidence: 99%

64Gb/s NRZ/PAM4 Burst-Mode Optical Receiver Frontend with Gain Control, Offset Correction and Gain Decoupled from Bandwidth

Serunjogi

Rasras

Sanduleanu

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The paper proposes a receiver frontend operating at 64Gb/s with a bandwidth of 50GHz and transimpedance gain of 70dBΩ. It consists of a burst-mode transimpedance amplifier (TIA) distributed feedback voltage amplifiers and two offset control mechanisms. By using negative and positive feedback, the gain is decoupled from bandwidth. Realized in a 65nm CMOS LPE technology, the occupied real estate on chip is 2mm2. The measurement results show operation at 64Gb/s with PAM4 signals and NRZ signals.

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“…A high R load can reduce both P opt1 and P opt2 , although P opt2 dominates P opt1 up to the shot noise limit. As a reference, the black dashed line denotes the thermal noise limit for a CMOS-integrated PD-TIA circuit with a noise equivalent power (NEP) of 14 pA∕Hz 0.5 [16], which determines the required optical power of around −18 dBm. With R load 20 kΩ for a resistor-loaded PD, an optical power of −20 dBm or an optical energy of 1 fJ/bit for 10 Gbit/s is available, which are below those of a PD-TIA circuit.…”

Section: Research Articlementioning

confidence: 99%

Photonic-crystal nano-photodetector with ultrasmall capacitance for on-chip light-to-voltage conversion without an amplifier

Nozaki¹,

Matsuo²,

Fujii³

et al. 2016

Optica

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The power consumption of a conventional photoreceiver is dominated by that of the electric amplifier connected to the photodetector (PD). An ultralow-capacitance PD can overcome this limitation, because it can generate sufficiently large voltage without an amplifier when combined with a high-impedance load. In this work, we demonstrate an ultracompact InGaAs PD based on a photonic crystal waveguide with a length of only 1.7 μm and a capacitance of less than 1 fF. Despite the small size of the device, a high responsivity of 1 A/W and a clear 40 Gbit/s eye diagram are observed, overcoming the conventional trade-off between size and responsivity. A resistor-loaded PD was actually fabricated for light-to-voltage conversion, and a kilo-volt/watt efficiency with a gigahertz bandwidth even without amplifiers was measured with an electro-optic probe. Combined experimental and theoretical results reveal that a bandwidth in excess of 10 GHz can be expected, leading to an ultralow energy consumption of less than 1 fJ/bit for the photoreceiver. Amplifier-less PDs with attractive performance levels are therefore feasible and a step toward a densely integrated photonic network/processor on a chip.

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A 40 Gbps optical receiver analog front-end in 65 nm CMOS

Cited by 11 publications

References 6 publications

InGaAs/InAlAs Avalanche Photodiode With Low Dark Current for High-Speed Operation

InGaAs/InAlAs Avalanche Photodiode With Low Dark Current for High-Speed Operation

64Gb/s NRZ/PAM4 Burst-Mode Optical Receiver Frontend with Gain Control, Offset Correction and Gain Decoupled from Bandwidth

Photonic-crystal nano-photodetector with ultrasmall capacitance for on-chip light-to-voltage conversion without an amplifier

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