A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

Kim, Sang Gyun; Hong, Chaerin; Eo, Yun Seong; Kim, Jihoon; Park, Sung Min

doi:10.1109/jssc.2018.2886323

Cited by 31 publications

(31 citation statements)

References 16 publications

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“…OOK 90Gb/s@10 -5 B2B Tx 6-tap FFE [17] 55-nm BiCMOS Diff. PAM4 106Gb/s@2.09×10 -4 B2B AWG equalization [18] 65-nm CMOS Diff. OOK 32Gb/s B2B Nil [19] 28-nm CMOS S2D PAM4 112Gb/s@<10 -4 B2B Tx 3-tap FFE [21] 28-nm CMOS Single OOK 53Gb/s@<10 -12 B2B Nil…”

Section: Discussionmentioning

confidence: 99%

“…The transimpedance amplifier (TIA) typically included in optical receiver designs largely determines the overall sensitivity, operation speed, linearity performance and power consumption of the receiver module [13][14][15][16][17]. A number of optical receivers co-integrated with TIAs have been reported in the literature, the realisations of which were based on various technology platforms, including 250-nm, 130 T [13][14][15][16][17][18][19][20][21][22]. Owing to the higher dynamic range and transition frequency of the BiCMOS technology [23][24], most of the high-speed demonstrations of TIA-integrated optical receivers to date have been realised in BiCMOS processes.…”

Section: Introductionmentioning

confidence: 99%

“…However, only a few works have reported high-speed transmission using a standard CMOS-based optical receiver. 32-Gb/s transmission using a mirrored-cascode differential TIA fabricated in 65-nm CMOS technology was reported in [18]. A 53-Gbit/s optical receiver co-integrated with a 28-nm CMOS TIA was demonstrated in [21], which achieved an energy efficiency of 0.65 pJ/bit.…”

Section: Introductionmentioning

confidence: 99%

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High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

Hong

Lacava

et al. 2021

J. Lightwave Technol.

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We report >100-Gb/s direct-detection (DD) transmission using an integrated silicon optical receiver, which comprised a fully-differential 28-nm complementary metal-oxide-semiconductor (CMOS) transimpedance amplifier (TIA) wire-bonded to a Silicon-Germanium (SiGe) balanced photodiode (PD). The fully-differential TIA architecture enabled significant bit-error-rate (BER) and signal-to-noise ratio improvements over a single-output TIA design when introducing it to the DD transmission. We experimentally validated its effectiveness in both back-to-back (B2B) and 2-km long standard single-mode fibre (SSMF) links using 50/100-Gb/s signals, including Nyquist on-off keying (OOK), Nyquist 4-ary pulse amplitude modulation (PAM4), uniformly-loaded DD optical orthogonal frequency division multiplexing (DDO-OFDM) and adaptively-loaded DDO-OFDM. Furthermore, we demonstrate that the integrated optical receiver was capable of balancing the trade-off between its electrical bandwidth and transimpedance gain by simply adjusting a voltage supply to the TIA. Without the need for optical amplification and while keeping the BERs below the 7% forward error correction limit, up to 173.22-Gb/s and 139.86-Gb/s adaptively-loaded DDO-OFDM transmission was achieved for B2B and 2-km transmission, respectively. The demonstrated results highlight the potential of the integrated silicon optical receiver, fabricated using the standard CMOS process for high-speed and short-reach optical interconnects.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

Hong

Lacava

et al. 2021

J. Lightwave Technol.

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“…In recent years, several CMOS based TIA designs [7][8][9][10] have been proposed. In [8], regulated with an on-chip voltage regulator which was powered from a 2.5V supply, a 112Gb/s PAM4 TIA built upon a 28nm CMOS process was reported with an optical sensitivity down to -5.1dBm.…”

Section: Published Bymentioning

confidence: 99%

Co-design of a differential transimpedance amplifier and balanced photodetector for a sub-pJ/bit silicon photonics receiver

Li¹,

Liu²,

Ruan³

et al. 2020

Opt. Express

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This paper presents the design and implementation of a fully differential optical receiver, which is aimed for short reach intensity modulation and direct detection (IMDD) transceiver links. A Si-Ge balanced photodetector (PD) has been co-designed and packaged with a novel differential transimpedance amplifier (TIA). The TIA design is realized with a standard 28nm CMOS process and operates with a standard digital supply (1V). Without using any equalization or DSP techniques, the proposed receiver can operate up to 54Gb/s with a BER less than the KP4 limit (2.2×10 -4 ) under an optical modulation amplitude (OMA) of -8.6dBm, while the power efficiency has been optimized to 0.55pJ/bit (0.98pJ/bit if output buffer is included).

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“…Recently, 100-Gigabit Ethernet (100 GbE) systems have received a great deal of attention [23]. Although quad 25-Gb/s per channel circuits can be a feasible solution in practice, there is still a need to increase the per channel bandwidth further so that a single-channel 100-Gb/s operation can be ultimately realized.…”

Section: High-speed Cmos Receiver Icsmentioning

confidence: 99%

CMOS Integrated Circuits for Various Optical Applications

Park¹

2020

Integrated Circuits/Microchips

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This chapter presents several CMOS integrated circuits (ICs) realized for various optical applications such as high-definition multimedia interface (HDMI), light detection and ranging (LiDAR), and Gigabit Ethernet (GbE). First, 4-channel 10-Gb/s per channel optical transmitter and receiver array chipset implemented in a 0.13-μm CMOS process are introduced to realize a 10-m active optical cable for HDMI 2.1 specifications. Second, a 16-channel optical receiver array chip is realized in a 0.18-μm CMOS technology for LiDAR applications. Third, a 40-GHz voltagemode mirrored-cascode transimpedance amplifier (MC-TIA) is implemented in a 65-nm CMOS for a feasible 100-GbE application. Even with advanced nano-CMOS technologies, we have suggested novel circuit techniques for optimum performance, such as input data detection (IDD) for low power, feedforward and asymmetric preemphasis for high speed, double-gain feedforward for high gain, selectable equalizer (SEQ) for specific bandwidth, mirrored-cascode for fully differential topology, etc. We believe that these novel circuit techniques help to achieve low-cost, low-power solutions for various optical applications.

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A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

Cited by 31 publications

References 16 publications

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

Co-design of a differential transimpedance amplifier and balanced photodetector for a sub-pJ/bit silicon photonics receiver

CMOS Integrated Circuits for Various Optical Applications

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