A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology

Chu, Michael; Philip, J.; Kim, Jin-Woo; LeRoy, Mitchell R.; Kraft, R.P.; McDonald, J. F.

doi:10.1109/jssc.2009.2039375

Cited by 43 publications

(16 citation statements)

References 13 publications

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“…For instance, Fujitsu Inc. recently introduced a 65 GSa/s ADC in CMOS [1]. Prior to that, Nortel Inc. had demonstrated a 40 GSa/s CMOS ADC [2], and Rensselaer Polytechnic Institute had introduced its 40 GSa/s SiGe ADC [3]. While radio frequency (RF) electronic data converters are now running at unprecedented sampling rates, their performance, as defined by effective number of bits (ENOB), has not improved commensurately.…”

Section: Introductionmentioning

confidence: 99%

Photonic ADC: overcoming the bottleneck of electronic jitter

Khilo¹,

Spector²,

Grein³

et al. 2012

Opt. Express

426

229

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Accurate conversion of wideband multi-GHz analog signals into the digital domain has long been a target of analog-to-digital converter (ADC) developers, driven by applications in radar systems, software radio, medical imaging, and communication systems. Aperture jitter has been a major bottleneck on the way towards higher speeds and better accuracy. Photonic ADCs, which perform sampling using ultra-stable optical pulse trains generated by mode-locked lasers, have been investigated for many years as a promising approach to overcome the jitter problem and bring ADC performance to new levels. This work demonstrates that the photonic approach can deliver on its promise by digitizing a 41 GHz signal with 7.0 effective bits using a photonic ADC built from discrete components. This accuracy corresponds to a timing jitter of 15 fs -a 4-5 times improvement over the performance of the best electronic ADCs which exist today. On the way towards an integrated photonic ADC, a silicon photonic chip with core photonic components was fabricated and used to digitize a 10 GHz signal with 3.5 effective bits. In these experiments, two wavelength channels were implemented, providing the overall sampling rate of 2.1 GSa/s. To show that photonic ADCs with larger channel counts are possible, a dual 20-channel silicon filter bank has been demonstrated. 289-296 (1992). 11. J. Kim, J. Chen, J. Cox, and F. X. Kärtner, "Attosecond-resolution timing jitter characterization of free-running mode-locked lasers using balanced optical cross-correlation," Opt. Lett. microwave signals at 40-GHz with higher than 7-ENOB resolution," Opt. ©2012 Optical Society of America

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Section: Introductionmentioning

confidence: 99%

Photonic ADC: overcoming the bottleneck of electronic jitter

Khilo¹,

Spector²,

Grein³

et al. 2012

Opt. Express

426

229

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“…The BiCMOS SRAMs can also be utilised in the analogue-to-digital converter (ADC) systems. In paper [27], a 40 GS/s time interleaved ADC using SiGe BiCMOS technology is achieved. BiCMOS SRAMs can be integrated into this system to store the interleaved multi-way sampling data for post-processing or calibration.…”

Section: Introductionmentioning

confidence: 99%

Design of BiCMOS SRAMs for high‐speed SiGe applications

LeRoy

Clarke

Chu

et al. 2014

IET Circuits, Devices & Systems

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This study documents the speeds of various SRAM buffer memories that are possible in a contemporary fast SiGe heterojunction bipolar transistor (HBT) BiCMOS process. An SRAM in a 0.13 µm HBT BiCMOS technology using current mode logic (CML)-style circuits serves as a basis for the discussion. This basic SRAM design features a CML decoder, CML word line driver, bipolar sense amplifier for achieving high speed and CMOS 6T memory cells for high density. The BiCMOS technology is especially useful for realising ultra-high-speed SRAMs for low level cache memory in high-clock rate computer systems, but when reorganised can also be utilised in analogue-to-digital converter (ADC) systems to store digitalised data. Speed and power tradeoffs can be made using different bias strategies, CML logic levels and different generations of SiGe HBTs. A demonstrated 128 kb SRAM macro consumes 2.7 W at 4 GHz using a −3.4 and −1.5 V supply voltage for the bipolar and CMOS circuits, respectively, and has dimensions of 3.5 mm × 3.6 mm by using IBM 8HP SiGe technology, which provides an HBT with a f T of 210 GHz. This macro can be integrated into large scale, ultra-wide bus SRAMs using heterogeneous silicon and 3D technology. Simulation indicates that with the next generation of SiGe HBTs, this SRAM macro can operate at 5 GHz, while consuming the same amount of power or alternatively consume 0.73 W, which is 73% less power consumption compared to 8HP, while operating with the same frequency of 4 GHz. Reorganising the memory for a 4 way-interleaved ADC, it can accept data written at 9.5 GS/s for 8HP designs, and 11.9 GS/s for 8XP designs.

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“…But such ADCs are a technical and economical challenge [1] due to the fundamental operating speed limit of electronic devices and clock (as well as aperture) jitters [2]. For instance, it is estimated that a clock jitter of *1 ps or better is needed for a 20 Gs/s sampling rate operation with a maximum 4-b resolution [3]. Thus, exploiting the femtosecond jitter of mode-locked laser pulse trains, optical timestretch approaches [4] and optical down-sampling strategies [5] have been under intensive investigation with 1-10 Ts/s real-time digitization and 40 GHz ADCs (7-ENOB resolution) reported, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, efforts with high-speed compound semiconductor technologies (e.g. InP HBT technologies [6]) and SiGe BiCMOS processes [3,7] have achieved sampling rates up to 40 Gs/s while using external clock signals. Yet, such technologies are more expensive than digital CMOS technologies that are dominating in semiconductor electronics.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, these high-speed ADC methods, which are currently the main high-speed CMOS ADC schemes, require highspeed and low-jitter clock signals [11]. Such clock generators, which determine the achievable ADC sampling rates and resolutions, are very difficult to implement on-chip [3]. Thus, it is intriguing to explore new avenues that can help solve clock generation and clock jitter problems in order to further boost CMOS ADC sampling rates and resolutions.…”

Section: Introductionmentioning

confidence: 99%

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A high-speed sample-and-hold circuit based on CMOS transmission lines

Wang

Gao

et al. 2010

Analog Integr Circ Sig Process

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We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 lm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of *50 ps width with *17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Gigasample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.

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A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology

Cited by 43 publications

References 13 publications

Photonic ADC: overcoming the bottleneck of electronic jitter

Photonic ADC: overcoming the bottleneck of electronic jitter

Design of BiCMOS SRAMs for high‐speed SiGe applications

A high-speed sample-and-hold circuit based on CMOS transmission lines

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