A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit

Kang, Kiseo; Minn, Donggyu; Bae, Seongun; Lee, Jaeho; Kang, Seokhyeong; Lee, Moonjoo; Song, Ho-Jin; Sim, Jae‐Yoon

doi:10.1109/jssc.2022.3198663

Cited by 19 publications

(5 citation statements)

References 39 publications

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“…21 were measured using a Keysight N1094B sampling scope without using additional equalization or de-embedding. The SRAM is programed with a 2 15 -length pseudorandom binary sequence (PRBS)-15 for NRZ and a quarternary QPRBS-15 for PAM4. The maximum speeds with sufficient eye opening at a BER of <10 −15 are explored for different modulation schemes and operating temperatures.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…So far, cryo-CMOS circuits have been placed at the 4-K stage to control and read out the qubits [14], [15], [16], [17], [18], [19], while (de)multiplexers are designed for operating at the mK stage to reduce the amount of interconnect between qubit and controller [20], [21]. Moreover, hot qubits operating with high gate fidelities at temperatures above 1 K are being developed to completely close the temperature gap between the electronics and qubits, thus improving the scalability of future quantum computers [22], [23].…”

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confidence: 99%

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A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

Fakkel,

Mortazavi,

Overwater

et al. 2024

IEEE J. Solid-State Circuits

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Addressing the advancement toward large-scale quantum computers, this article presents the first four-level pulse amplitude modulation (PAM4) wireline transmitter (TX) operating at cryogenic temperatures (CTs). With quantum computers scaling up toward thousands of quantum bits (qubits), but having too limited fidelity for robust operation, continuous rounds of quantum error correction (QEC) are necessary. However, QEC requires a large amount of data to be transferred from a cryogenic controller at 4 K to a classical processor at room temperature (RT). To bridge the gap, a high-speed data link between the quantum processor at CT and the classical counterpart at RT is needed. The proposed PAM4 TX architecture integrates a low-power 64:4 serializer structure, a high-speed 4:1 currentmode logic (CML) multiplexer, and a linear 6-bit digital-to-analog converter (DAC). Considering the challenges and benefits of CMOS operating at CTs, the TX architecture and circuitry are designed to exploit the maximum speed, while maintaining sufficient linearity. The fabricated 40-nm CMOS chip achieves a data rate of 40-Gb/s (36-Gb/s), an energy efficiency of 2.46 pJ/b (2.47 pJ/b), and 97.8% (96.6%) ratio of level mismatch (RLM) at CT (RT). While demonstrating an energy efficiency comparable to prior-art TXs in more advanced CMOS nodes at RT, the broad operating temperature of the proposed TX enables the required high-speed wireline link for large-scale quantum computers.

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Section: Measurement Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

Fakkel,

Mortazavi,

Overwater

et al. 2024

IEEE J. Solid-State Circuits

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“…Fig. 18 shows the SNR for different T sys and T int values when the system is probed at its maximum achievable A sig (P RF = -95 dBm) while considering a T amb of 4 K. Assuming a modest T sys of 50 K based on the recently published cryo-CMOS RX design [23], [29]- [32], the contour plot reveals that the prior-art cryo-CMOS receivers cannot satisfy the 11.5 dB target SNR at a T int of 1 µs. As it is suspected that the noise performance of the cryo-CMOS receivers is limited by the shot noise [33] and the self-heating effect [34], passive amplification techniques should be investigated in the future to avoid large biasing currents required for active devices in LNAs [35], [36].…”

Section: Noise Temperature Requirement For Readout Electronicsmentioning

confidence: 99%

Modeling and Experimental Validation of the Intrinsic SNR in Spin Qubit Gate-Based Readout and Its Impacts on Readout Electronics

Prabowo,

Dijkema,

Xue

et al. 2024

IEEE Trans. Quantum Eng.

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In semiconductor spin quantum bits (qubits), the radio-frequency (RF) gate-based readout is a promising solution for future large-scale integration, as it allows for a fast, frequency-multiplexed readout architecture, enabling multiple qubits to be read out simultaneously. This paper introduces a theoretical framework to evaluate the effect of various parameters, such as the readout probe power, readout chain's noise performance, and integration time on the intrinsic readout signal-to-noise ratio (SNR), and thus readout fidelity of RF gate-based readout systems. By analyzing the underlying physics of spin qubits during readout, this work proposes a qubit readout model that takes into account the qubit's quantum mechanical properties, providing a way to evaluate the trade-offs among the aforementioned parameters. The validity of the proposed model is evaluated by comparing the simulation and experimental results. The proposed analytical approach, the developed model, and the experimental results enable designers to optimize the entire readout chain effectively, thus leading to a faster, lower-power readout system with integrated cryogenic electronics.

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“…For example, [108] proposed a cryo-CMOS qubit controller fabricated in Intel 22-nm FinFET technology, and its power consumption is several hundred mW. However, as superconducting transmon qubits operate below 100 mK, dilution refrigerators offer insufficient cooling power for these electronic circuits at that temperature (as discussed above), although recent efforts propose an electronic interface for transmons operating at 4 K [111,112]. Alternatively, semiconductor spin qubits can operate at temperatures above 1 K [113], where the power budget is enough for system on a chip (SoCs) [108][109][110], making them in principle compatible with standard CMOS processing.…”

Section: Opportunities At Cryogenic Temperaturementioning

confidence: 99%

Real-time decoding for fault-tolerant quantum computing: progress, challenges and outlook

Battistel¹,

Chamberland

Johar

et al. 2023

Nano Futures

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Quantum computing is poised to solve practically useful problems which are computationally intractable for classical supercomputers. However, the current generation of quantum computers are limited by errors that may only partially be mitigated by developing higher-quality qubits. Quantum error correction~(QEC) will thus be necessary to ensure fault tolerance. QEC protects the logical information by cyclically measuring syndrome information about the errors. An essential part of QEC is the decoder, which uses the syndrome to compute the likely effect of the errors on the logical degrees of freedom and provide a tentative correction. The decoder must be accurate, fast enough to keep pace with the QEC~cycle (e.g., on a microsecond timescale for superconducting qubits) and with hard real-time system integration to support logical operations. As such, real-time decoding is essential to realize fault-tolerant quantum computing and to achieve quantum advantage. In this work, we highlight some of the key challenges facing the implementation of real-time decoders while providing a succinct summary of the progress to-date. Furthermore, we lay out our perspective for the future development and provide a possible roadmap for the field of real-time decoding in the next few years. As the quantum hardware is anticipated to scale up, this perspective article will provide a guidance for researchers, focusing on the most pressing issues in real-time decoding and facilitating the development of solutions across quantum and computer science.

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A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit

Cited by 19 publications

References 39 publications

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing

Modeling and Experimental Validation of the Intrinsic SNR in Spin Qubit Gate-Based Readout and Its Impacts on Readout Electronics

Real-time decoding for fault-tolerant quantum computing: progress, challenges and outlook

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