A 400-mhz processor for the conversion of rectangular to polar coordinates in 0.25-μm cmos

Hwang, D.; Fu, Dengwei; Willson, A.N.

doi:10.1109/jssc.2003.817588

Cited by 29 publications

(17 citation statements)

References 13 publications

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“…The coarse-fine rotation approach in some modified forms has been applied for reduced-latency implementation of sine and cosine generation [24]- [28], high-speed and high-precision rotation [24], [26], and conversion of rectangular to polar coordinates and vice versa [29], [30].…”

Section: Hybrid or Coarse-fine Rotation Cordicmentioning

confidence: 99%

“…It is shown in [55] that the MSR technique can significantly reduce the total iteration count so as to improve the speed performance and enhance the signal-to-quantization-noise ratio (SQNR) performance by controlling the internal dynamic range. The MSR-CORDIC scheme has been applied to a variable-length FFT processor design [29], and found to result in significant hardware reduction in the implementation of twiddle-factor multiplications. Although, the interleaved scaling and MSR-CORDIC provide hardware reduction, they also lead to the reduction of throughput.…”

Section: A Implementation Of Mixed-scaling-rotationmentioning

confidence: 99%

“…Givens rotation is an orthogonal transformation of the form (29) where and . The QR decomposition requires two types of iterative operations to obtain an upper-triangular matrix using orthogonal transformations.…”

Section: A Matrix Computation 1) Qr Decompositionmentioning

confidence: 99%

See 2 more Smart Citations

50 Years of CORDIC: Algorithms, Architectures, and Applications

Meher

Valls

Juang

et al. 2009

IEEE Trans. Circuits Syst. I

457

198

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Section: Hybrid or Coarse-fine Rotation Cordicmentioning

confidence: 99%

Section: A Implementation Of Mixed-scaling-rotationmentioning

confidence: 99%

See 1 more Smart Citation

50 Years of CORDIC: Algorithms, Architectures, and Applications

Meher

Valls

Juang

et al. 2009

IEEE Trans. Circuits Syst. I

457

198

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“…In many digital communication applications, the efficient Rectangular to Polar conversion (RPC) is necessary [1], [2]. A polar modulation offers an alternative for multimode and multiband operations [3].…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Design of Rectangular to Polar Converter using Linear Convergence

Agrawal¹,

Mehra²

2012

IJCA

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In recent years, the growth of multimedia services and applications in digital data transmission has led to ever increasing demands of effective data transmission over the wired as well as wireless communication systems. Since digital communication systems need to deal with multimode and multiband operations on complex signals many-a-times, there is always a requirement of an efficient method for rapid phase and magnitude extraction. The proposed Rectangular to Polar Converter (RPC) has been implemented using fully parallel CORDIC, a Linear Convergence Algorithm, in vectoring mode. The design is synthesized with ISE 10.1 software, and implemented on 2v3000fg676-4. Synthesis results show that the design is able to work at 177.620 MHz with less hardware requirements. General TermsA rectangular to polar conversion is required so that transmitters must accommodate constant envelop signals as well as non-constant envelop signals to achieve multimode and multiband operations. In burst-mode communication systems, a rapid carrier is crucial. Hence a fast rectangular-topolar conversion is needed. Delay-matching of phase as well as amplitude is crucial so that the restoration of the transmitted data at the receiver may be not be imperfect if the delays are unmatched.

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“…Arquitecturas en las cuales se intenta reducir el consumo de potencia han sido propuestas por [43], utilizando para ello interpoladores lineales e implementando la división de las dos entradas mediante un divisor paralelo non-restoring. Hwang y otros presentan en [44] una arquitectura que aproxima la atan(y/x) dividiendo el cálculo en dos etapas, utilizando para ello LUTs y multiplicadores de reducido tamaño. A continuación pasamos a presentar nuestra arquitectura hardware para la aproximación de la atan(y/x).…”

Section: Introductionunclassified

Implementaciones de Funciones Elementales en Dispositivos FPGA

Mazon¹

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In this thesis we have designed several hardware architectures of some typical digital subsystems for high performance communications systems, aiming at optimized implementations for these systems. The work has focused on two areas: the approximation of elementary functions, specifically the logarithm and arctangent, and the design of an emulator of additive Gaussian noise channel. The architectures have been designed at all times with the objective to achieve an efficient implementation in Field Programmable Gate Arrays devices (FPGAs), due to its increasing use in digital high performance communications systems. For the approximation of logarithm we have proposed two different architectures, one based on the use of multipartite table methods and the other based on the Mitchell's approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that corrects the piecewise interpolation error. A first architecture for the approximation of atan(y/x) is based on the computation of the reciprocal of x and the arctangent approximation, using multipartite Look-up tables (LUTs). This proposal reduces the power consumption compared to the best techniques described in the literature, such based on CORDIC. A second strategy for the approximation of atan(y/x) is based on logarithmic transformations, which transforms the calculation of the division of two inputs in a simple subtraction and requires the computation of atan(2 w ). This second strategy has resulted in two architectures, a first in which both the logarithm and atan(2 w ) have been implemented using multipartite LUTs, also combined with the use of non-uniform segmentation techniques in the calculation of atan(2 w ), and a second architecture using a piecewise linear interpolation with power-of-two slopes and correction tables. The results obtained with this strategy improve the first architecture discussed. Two architectures for the approximation of arctangent and one for the logarithm have resulted in three publications in internationals journals. We also have proposed several architectures for a Gaussian white noise generator. The designs are based on the Inversion method, specifically approximating the inverse of cumulative distributions functions by polynomial interpolation and non-uniform segmentation. These architectures offer its output a standard deviation of ±13.1σ and 13 fractional bits, higher values than practically all hardware generators present in the literature, employing, in comparison, fewer FPGA resources. Compared to Gaussian channel implementations based on the inversion method presented by other authors, our architectures achieve a significant reduction in area partially or completely eliminating the barrel-shifter. The results for Gaussian channel emulator have been sent to an international journal, being currently under review process.

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A 400-mhz processor for the conversion of rectangular to polar coordinates in 0.25-μm cmos

Cited by 29 publications

References 13 publications

50 Years of CORDIC: Algorithms, Architectures, and Applications

50 Years of CORDIC: Algorithms, Architectures, and Applications

Reconfigurable Design of Rectangular to Polar Converter using Linear Convergence

Implementaciones de Funciones Elementales en Dispositivos FPGA

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