A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

Amamiya, Y.; Kaeriyama, Shunichi; Noguchi, Hidemi; Yamazaki, Z.; Yamase, Tomoyuki; Hosoya, K.; Okamoto, Minoru; Tomari, S.; Yamaguchi, H.; Shoda, H.; Ikeda, Hidetoshi; Tanaka, Shōji; Tomoaki, Takahashi; Ohhira, R.; Noda, Akiko; Hijioka, K.; Tanabe, A.; Fujita, Shin; Kawahara, N.

doi:10.1109/isscc.2009.4977456

Cited by 12 publications

(6 citation statements)

References 7 publications

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“…This enables the use of DQPSK for communication over longer distances on legacy fiber. The 3W power consumption is less than 25% of a first generation biCMOS SFI5 SERDES chipset [2], [3] and 45% less than a recent CMOS SFI5 SERDES chipset [9]. In addition, minimal use of inductors and adoption of the more recent SFI5.2 standard results in chip area more than 1/3 less than [9].…”

Section: Discussionmentioning

confidence: 99%

A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

Nedovic

Kristensson

Parikh

et al. 2009

2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium

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A 2 x 21.5-22.3 Gb/s to 4 x 10.7-11.2 Gb/s SFI5.2 compliant two-chip SerDes for a 40 Gb/s optical transponder module has been fabricated in 65 nm 12-metal CMOS. The deserializer receives 2 x 20 Gb/s data from a TIA and outputs SFI 5.2 4 x 10 Gb/s data and 10 Gb/s deskew channel. The serializer receives SFI5.2 inputs and outputs 2 x 20 Gb/s for the optical DQPSK modulator. Although inductor-peaked CML is needed in the deserializer 20 Gb/s input limiting amplifier (LA) and the serializer output stages, power reduction to 3 W for both IC's is effected by deserializing to 16 x 2.5 Gb/s internally and implementing the core logic using standard CMOS circuits.

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Section: Discussionmentioning

confidence: 99%

A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

Nedovic

Kristensson

Parikh

et al. 2009

2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium

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“…However, the interconnect partially takes advantage of the technology scaling, because faster transistors enable a better circuit to overcome the increased channel loss. Figure 11A shows a survey from the state-of-the-art published works ( Tamura et al, 2001 ; Haycock & Mooney, 2001 ; Tanaka et al, 2002 ; Lee et al, 2003 , 2004 ; Krishna et al, 2005 ; Landman et al, 2005 ; Casper et al, 2006 ; Palermo, Emami-Neyestanak & Horowitz, 2008 ; Kim et al, 2008 ; Lee, Chen & Wang, 2008 ; Amamiya et al, 2009 ; Chen et al, 2011 ; Takemoto et al, 2012 ; Raghavan et al, 2013 ; Navid et al, 2014 ; Zhang et al, 2015 ; Upadhyaya et al, 2015 ; Norimatsu et al, 2016 ; Gopalakrishnan et al, 2016 ; Shibasaki et al, 2016 ; Peng et al, 2017 ; Han et al, 2017 ; Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ), where we can confirm the correlation between the technology node and the data rate. On the other hand, however, overcoming the increased channel loss has become more and more expensive as the loss is going worse as the bandwidth increases; the equalization circuits consume too much power to compensate the loss, which makes people hesitant to increase the bandwidth.…”

Section: Interconnectmentioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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“…To ensure sufficient speed, the CML DFFs used inductive peaking. Small area inductors are achieved by using three‐dimensional solenoid‐shaped inductors, created from two thick metal layers and another three routing metal layers [6]. An inductor value of 910 pH was realised in a 38 × 38 µm 2 footprint, including a guard ring and metal dummies.…”

Section: Circuit Implementationmentioning

confidence: 99%

Driver circuit for a PAM‐4 optical transmitter using 65 nm CMOS and silicon photonic technologies

Zhou

Sadeghipour

et al. 2016

Electron. lett.

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A push-pull silicon photonic Mach-Zehnder modulator (MZM) driver is presented which uses a switched capacitor approach to generate a ∼2 V peak-to-peak differential 4-level pulse amplitude modulation (PAM-4) signal. The driver chip includes a Gray encoder and retiming flip-flops. The switched capacitor approach allows driving the lumped silicon photonic MZM with reduced power consumption compared with the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400 Gbit/s 802.3 Ethernet. The chip was fabricated using a 65 nm CMOS technology and flipchipped on top of the silicon photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4 dB extinction ratio for a 36 Gbit/s (18 Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of 0.11 mm 2 and consumes 236 mW from 1.2 to 2.4 V supply voltages. This corresponds to an energy efficiency of 6.55 pJ/bit including Gray encoder and retiming, or 5.37 pJ/bit for the driver circuit only.

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A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

Cited by 12 publications

References 7 publications

A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

A 2x22.3Gb/s SFI5.2 SerDes in 65nm CMOS

Today’s computing challenges: opportunities for computer hardware design

Driver circuit for a PAM‐4 optical transmitter using 65 nm CMOS and silicon photonic technologies

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