A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer

Abstract

This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCO's distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms of nonlinearity. Fabricated in a 40nm CMOS process, the prototype two-step 12-bit ADC achieves 68.7dB/66.8dB SNR/SNDR with a 40MHz bandwidth and consumes only 4.98mW. This corresponds to an excellent FoM of 35fJ/step.

A 40-MHz Bandwidth 0–2 MASH VCO-Based Delta-Sigma ADC With 35-fJ/Step FoM

“…The chip microphotograph is shown in [6]. The core circuit occupies an active area of only 0.16 mm 2 .…”

“…The clock timing will be discussed in section III in detail. Nonlinearity exists in different blocks, but it is mitigated in this design at both architecture and circuit levels [6]. Compared to this design, although the 2 nd -stage output in [14] is free from distortion, no cancellation exists to ameliorate the first-stage quantizer's nonlinearity.…”

“…Similar to the quantization noise, the nonlinearity of the first stage can also be cancelled in the cascaded structure [6], [9]. In addition, as the second stage only processes the noise-shaped quantization noise, its inputvoltage swing is greatly reduced, resulting in a linear secondstage quantizer [3], [7], [9], [10].…”

“…Thanks to the 1 storder high-pass shaping, the proposed ADC is still robust and achieves 78-dB SFDR within ±10% gain variations. It is safe to say that, the 0-2 MASH VCO-based structure is much more insensitive to gain mismatch than the 0-1 MASH structure [6], [9].…”

“…In this paper, we propose a VCO-based 0-2 MASH ∆Σ ADC architecture with a novel dual-input VCO-based quantizer, a 40-MHz bandwidth (BW) 12-bit prototype with 66.8-dB SNDR and an excellent FoM of 35 fJ/step is achieved [6]. P. Zhu The paper is organized as follows.…”