A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting

Chang, Yung-Te; Wu, Min-Rui; Hsieh, Chih-Cheng

doi:10.1109/iscas.2019.8702449

Cited by 6 publications

(1 citation statement)

References 6 publications

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“…From Figure 16, it is observed that minimum power consumption is obtained from a new architecture of parallel and op-amp sharing technique when compared with the other techniques such as gain boosting, switched capacitor biasing and switched capacitor amplifier and so on (Naderi et al , 2019; Chang et al , 2019). The main cause for power reduction is that the reduction in the op-amps and the capacitors by processing a wide input signal range using two paths named as the main and secondary path which results in minimum power consumption in parallel sampling MDAC.…”

Section: Resultsmentioning

confidence: 99%

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

Sam

Paul

2021

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Purpose In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC. Design/methodology/approach Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique. Findings This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent. Originality/value Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

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Section: Resultsmentioning

confidence: 99%

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

Sam

Paul

2021

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A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

Sam

Moni

Paul

et al. 2021

Silicon

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This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp-p,diff input signal while consuming only 7.3mW power from 1.8V supply.

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An Overshoot Voltage Reduction Technique with Improved Speed for Zero-Crossing Detector in Pipeline ADCs

Kunnatharayil

Gogebakan

Ceylan

et al. 2022

2022 IEEE International Symposium on Circuits and Systems (ISCAS)

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A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting

Cited by 6 publications

References 6 publications

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

An Overshoot Voltage Reduction Technique with Improved Speed for Zero-Crossing Detector in Pipeline ADCs

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