A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems

Chang, Muya; Spetalnick, Samuel; Crafton, Brian; Khwa, Win-San; Chih, Yu-Der; Chang, Meng-Fan; Raychowdhury, Arijit

doi:10.1109/isscc42614.2022.9731679

Cited by 34 publications

(10 citation statements)

References 4 publications

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“…The cluster's peak computational efficiency reaches 1.6 TOPS/W, higher than other SOA PULP architectures [36], as seen in Table 3. Although the PULP cluster is not equipped with any accelerator engine, it achieves 8-bit peak efficiency comparable to SOA architectures [36][37][38] and outperforms peak performance SOA PULP systems [36] by a factor of 2.7×.…”

Section: Linear Regression For Eye Movement Trackingmentioning

confidence: 99%

Kraken: An Open-Source RISC-V SoC for Ultra-Low Power Multi-Modal Perception

Potocnik,

Mauro,

Leitner

et al. 2024

Preprint

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We introduce Kraken, a highly flexible heterogeneous system-on-chip (SoC) fabricated in 22 FDX technology demonstrating leading-edge energy efficiency and computational capabilities for ultra-low power extreme-edge applications. Inspired by the multi-modal perception system of mammalians, Kraken supports multi-modal sensing and perception via event-based and sampling-based sensor interfaces coupled with a spiking neural network accelerator (SNE) and a ternary neural network accelerator (CUTIE), respectively. An octa-core 32-bit RISC-V cluster with ML and DSP extensions enables sensor fusion and flexible parallel data processing. A fabric controller (FC) featuring a dedicated core manages all compute subsystems and low computation intensity tasks. We analyzed Kraken’s performance and efficiency: SNE consumes 2.6 pJ/SOp and 470 μJ/inference for eye gaze prediction with 64% accuracy. CUTIE achieves 590 TOp/s/W and 2.72 μJ/inference for foveated object classification with 88% accuracy. The RISC-V cluster consumes 0.45 pJ per 8-bit MAC operation, and 12.01 μJ/inference for eye tracking with a mean average error of 0.24. All of Kraken’s subsystems improve upon the state-of-the-art (SOA), while the heterogenous architecture offers extreme flexibility in supporting ultra-low power multi-modal AI fusion applications.

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Section: Linear Regression For Eye Movement Trackingmentioning

confidence: 99%

Kraken: An Open-Source RISC-V SoC for Ultra-Low Power Multi-Modal Perception

Potocnik,

Mauro,

Leitner

et al. 2024

Preprint

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show abstract

“…Such implementation needs only resistors and can support input and weight with arbitrary resolution. Nonetheless, to avoid the sneak-path current issue and maintain better retention/reliability, practical RRAM-CIM macros are commonly implemented using a 1T1R array with binary cell-wise computation [10]- [13], [16]- [28], as illustrated in Fig. 2(a).…”

Section: Rram-based Cim Backgroundsmentioning

confidence: 99%

A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic Impedance Boosting and In-ADC Computing

Xie

2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Resistive random access memory (RRAM) is considered to be a promising compute-in-memory (CIM) platform; however, they tend to lose energy efficiency quickly in highthroughput and high-resolution cases. This paper proposes an analog-oriented RRAM array/read circuits co-design technique to solve the trade-offs between distortion, power consumption, throughput, and chip area. In previous works, the RRAM array is built in a digital mindset that access transistors only serve as switches. Instead, this work investigates a new perspective that utilizes access transistors as common-gate current buffers which reduce the operating current and amplify the output impedance. To further decrease the complexity of peripheral circuits, the idea of In-ADC Computing (IAC) is proposed, which performs shift-add operation together with analog-to-digital conversion. Benefiting from proposed ideas, a pre-trained VGG-8 network based on the CIFAR-10 dataset can be implemented and an accuracy of 87.2% is achieved with 8.9 TOPS/W energy efficiency (for 8-bit MAC operation), demonstrating that the proposed techniques enable low-distortion partial sum results while still be able to operate in a power-efficient way.

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“…The efficient integration of various types of IMC hardware together is also necessary. There has been a successful attempt to combine an RRAM-based IMC accelerator with conventional SRAM-based memories and embedded processor [72]. The efficient integration of non-volatile memories with traditional memories, e.g.…”

Section: G Integration Of Imc Architectures To Traditional Hardware D...mentioning

confidence: 99%

Towards Efficient In-Memory Computing Hardware for Quantized Neural Networks: State-of-the-Art, Open Challenges and Perspectives

Krestinskaya

Zhang

Salama

2023

IEEE Trans. Nanotechnology

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The amount of data processed in the cloud, the development of Internet-of-Things (IoT) applications, and growing data privacy concerns force the transition from cloud-based to edge-based processing. Limited energy and computational resources on edge push the transition from traditional von Neumann architectures to In-memory Computing (IMC), especially for machine learning and neural network applications. Network compression techniques are applied to implement a neural network on limited hardware resources. Quantization is one of the most efficient network compression techniques allowing to reduce the memory footprint, latency, and energy consumption. This paper provides a comprehensive review of IMC-based Quantized Neural Networks (QNN) and links software-based quantization approaches to IMC hardware implementation. Moreover, open challenges, QNN design requirements, recommendations, and perspectives along with an IMC-based QNN hardware roadmap are provided.

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A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems

Cited by 34 publications

References 4 publications

Kraken: An Open-Source RISC-V SoC for Ultra-Low Power Multi-Modal Perception

Kraken: An Open-Source RISC-V SoC for Ultra-Low Power Multi-Modal Perception

A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic Impedance Boosting and In-ADC Computing

Towards Efficient In-Memory Computing Hardware for Quantized Neural Networks: State-of-the-Art, Open Challenges and Perspectives

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