A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Guo

Luan

et al. 2019

“…The I-SAR ADC needs no static power consumption for the residue interpolation. A 12 b 200 MS/s prototype ADC demonstrates the feasibility of the new architecture [22].…”

Section: Introductionmentioning

confidence: 95%

“…Ring amplifiers [15,16] have the advantage of lower power consumption and process scalability, but the design complexity increases to achieve high DC gain for accurate inter-stage gain. To avoid the accurate gain requirement of the RA, dual-residue pipelining schemes have been proposed [17][18][19][20][21][22][23]. Because the conversion scheme uses the ratio of the two residues to find the LSB code, it is important that the two residues are amplified by the same gain value.…”

Section: Introductionmentioning

confidence: 99%

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Seo

2021

Self Cite

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

“…In order to realize a low-power TI ADC of several tens of GS/s, a single channel ADC used as a sub-ADC must be designed to be very compact and high-speed. During the past decade, successive approximation register (SAR) analog-to-digital converters (ADCs) have become a dominant ADC architecture as sub-ADCs of the TI ADC, covering a wide range of resolution and speed owing to advanced process technologies, mostly attributed to their digital friendly architecture [4][5][6][7][8][9][10][11]. The need for high-speed clocks for internal loop operation in a synchronous SAR ADC can be eliminated by using asynchronous architecture [12][13][14].…”

Section: Introductionmentioning

confidence: 99%

A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

2022

This paper presents a high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that takes advantage of both asynchronous SAR ADC and loop-unrolled (LU) SAR ADC. By utilizing the output of the dynamic amplifier (DA) to generate an asynchronous clock, the reset time for the DA can be hidden behind the comparator latching time. Dedicated latches for each digital-to-analog converter (DAC) element eliminate the need for DAC switching logic. The proposed inverter-inserted three-stage comparator significantly reduces the input-referred offset of the comparator. The prototype 6-bit 700 MS/s SAR ADC was implemented in a 28 nm CMOS process and has a small 0.0012 mm2 area. The measured peak DNL and INL without any mismatch calibration were 0.33 and 0.27 LSB, respectively. With Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) were 34.07 and 47.52 dB, respectively. The power consumption was 1 mW under a supply voltage of 1.0 V, leading to a Walden figure of merit (FoM) of 34.6 fJ/conversion-step at 700 MS/s.