A 43-mW MASH 2-2 CT $\Sigma \Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS

Edward, Alexander; Liu, Qiyuan; Briseno-Vidrios, Carlos; Kinyua, Martin; Soenen, Eric; Karsilayan, A.I.; Silva-Martí­nez, J.

doi:10.1109/jssc.2016.2616361

Cited by 37 publications

(16 citation statements)

References 25 publications

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“…Owing to all-digital designing, employing the multirating technique and implementation on a high-speed FPGA board, the proposed TDC exhibited superior time-resolution, dynamic range and FoM than in previous works. Moreover, Table 1 reveals that this work represents an acceptable SNR compared with TDCs in [23][24][25] while they utilize higher order of noise-shaping, and higher SNR over the same order TDC in [22]. Therefore, we can surmise that higher SNR can be attained by increasing noise-shaping order via incorporating more stages to the proposed structure.…”

Section: Measured Resultsmentioning

confidence: 83%

“…Also, the aforementioned decoding takes three clock cycles to be completed which degrades the speed of TDC. In the meantime, advancing of CMOS technology on the one hand, and introducing high-performance FPGA chips on the other, have had an impressive impact on presenting fast, accurate and low power application specific integrated circuit (ASIC) and FPGA-based TDCs [22][23][24][25][26][27][28][29]. However, all-digital designing encourages some designers to implement their works on FPGA.…”

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confidence: 99%

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An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

et al. 2019

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An all-digital voltage-controlled oscillator (VCO)-based second-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC) is presented in this paper. The prototype of the proposed TDC was implemented on an Altera Stratix IV FPGA board. In order to improve the performance over conventional TDCs, a multirating technique is employed in this work in which higher sampling rate is used for higher stages. Experimental results show that the multirating technique had a significant influence on improving signal-to-noise ratio (SNR), from 43.09 dB without multirating to 61.02 dB with multirating technique (a gain of 17.93 dB) by quadrupling the sampling rate of the second stage. As the proposed design works in the time-domain and does not consist of any loop and calibration block, no time-to-voltage conversion is needed which results in low complexity and power consumption. A built-in oscillator and phase-locked loops (PLLs) of the FPGA board are utilized to generate sampling clocks at different frequencies. Therefore, no external clock needs to be applied to the proposed TDC. Two cases with different sampling rates were examined by the proposed design to demonstrate the capability of the technique. It can be implied that, by employing multirating technique and increasing sampling frequency, higher SNR can be achieved.

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Section: Measured Resultsmentioning

confidence: 83%

mentioning

confidence: 99%

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

et al. 2019

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“…To derive specifications for the op-amp, the acceptable percentage error has to be selected. A 15% error can be taken as the maximum acceptable error as it is a value comparable to resistor and capacitor variations due to process corners [5]. In that case, from Figure 3, we can see that at p 1 = f o , the deviation is reduced to less than 15% for A o larger than 34 dB i.e.…”

Section: Introductionmentioning

confidence: 94%

“…At this stage, with V GS , V DS , V S B , and L known, the DC gain can be fixed, using (5), independent of the current consumption of each stage [7].…”

Section: Design Of the Amplifiermentioning

confidence: 99%

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators

Gebreyohannes¹,

Louërat²,

Aboushady³

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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This work presents a 4 th-order multi-stage, multipath, feed-forward-compensated operational amplifier in 65 nm CMOS technology. It is designed to meet the requirements of a continuous-time bandpass Σ∆ modulator with multi-GHz sampling frequency. The designed amplifier is modular with each stage implemented based on a unit differential amplifier block and it meets its targets with smart placement of poles and zeros. The amplifier is simulated under the loading condition of a single-amplifier resonator which is in turn part of a 6 thorder Σ∆ modulator. The unloaded amplifier reaches a unitygain-frequency of 38.29 GHz and a DC gain of 58 dB. With a parallel load of 440 fF and 300 Ω, representing the maximum load, the op-amp, including common-mode and biasing circuits, consumes a total of 18.98 mA from a supply voltage of 1.2 V. It is unconditionally stable with a phase margin of 54 • and has gains of 35 dB and 23 dB at 1 GHz and 2 GHz respectively.

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“…A low-power comparator is attractive in energy-efficient successive approximation register (SAR) analog-to-digital converters (ADCs), especially for biomedical applications. Compared with conventional static comparators [1], dynamic comparators [2,3,4,5,6,7] are free of static power consumption, which is important to a full dynamic operating SAR ADC. Dynamic comparators also show faster conversion speed than time-domain comparators [8].…”

Section: Introductionmentioning

confidence: 99%

An energy-efficient SAR ADC using a single-phase clocked dynamic comparator with energy and speed enhanced technique

Zhang

Fan

2017

IEICE Electron. Express

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This paper presents an energy-efficient 500 kS/s 8-bit SAR ADC with a novel dynamic comparator. The proposed dynamic comparator employs a cross-coupling cascode based preamp and an inverter-based pseudo-latch. This approach achieves a 40% higher speed, a 24% lower power consumption, and a similar input-referred noise level, compared with a conventional double-tail dynamic comparator. Moreover, only one single phase clock is required for the proposed comparator. The prototype ADC was fabricated in a 0.5 µm CMOS process with an active area of 0.18 mm 2. Operating under a 1.8 V supply with Nyquist frequency input signal, the ADC consumes 18.2 µW at 500 kS/s and achieves SNDR and SFDR of 47.5 dB and 63.2 dB, respectively. Walden FoM of 188 fJ/conv.-step is achieved.

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A 43-mW MASH 2-2 CT $\Sigma \Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS

Cited by 37 publications

References 25 publications

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

Design of a 4th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators

An energy-efficient SAR ADC using a single-phase clocked dynamic comparator with energy and speed enhanced technique

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