A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video

Abstract

The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 μm CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.

A view scalable multi-view video decoder system

“…In this paper, we adopt a low memory bandwidth H.264 video decoder core [5][6][7][8] and propose a view-scalable multi-view video decoder system with a software/hardware co-design, which uses software to extract different view information from the multi-view video stream, and uses some hardware decoders to decode each view video at the same time. It extracts and identifies the different view information of the multi-view video stream after decoding multiview video bit-stream header by software.…”

“…2 [7][8]. We optimize the proposed design from both the viewpoints of system and components to make the best design trade-off to achieve the goals of high flexibility, high performance, and low cost.…”